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| ds07-13702-4e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90520 series MB90522/523/f523/v520 n description the mb90520 series is a general-purpose 16-bit microcontroller developed and designed by fujitsu for process control applications in consumer products that require high-speed real-time processing. the instruction set of the f 2 mc-16lx cpu core inherits at architecture of the f 2 mc* family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word data. the mb90520 series has peripheral resources of 8/10-bit a/d converter, 8-bit d/a converter, uart (sci), extended i/o serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit ppg timers 0 and 1, i/o timer (16-bit free-run timers 1 and 2, input captures 0 and 1 (icu), output compares 0 and 1 (ocu)), and an lcd controller/driver. *:f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz, 4 mhz to 16 mhz). the system can be operated by a sub-clock (rated at 32.768 khz). minimum instruction execution time: 62.5 ns (at oscillation of 4 mhz, four times the oscillation clock, operation at v cc of 5.0 v) (continued) n packages 120-pin plastic lqfp (fpt-120p-m05) 120-pin plastic qfp (fpt-120p-m13)
mb90520 series 2 (continued) ? maximum memory space 16 mbytes ? instruction set optimized for controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division instruction and reti instruction functions enhanced precision calculation realized by 32-bit accumulator ? instruction set designed for high level language (c) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed 4-byte instruction queue ? enhanced interrupt function 8 levels, 34 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os): up to 16 channels ? embedded rom size and types mask rom: 64 kbytes/128 kbytes flash rom: 128 kbytes ? embedded ram size mask rom: 4 kbytes flash rom: 4 kbytes evaluation product: 6 kbytes ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode hardware stand-by mode clock mode (mode in which other than sub-clock and timebase timer are stopped) ?process cmos technology ? i/o port general-purpose i/o ports (cmos): 53 ports general-purpose i/o ports (via pull-up resistors): 24 ports general-purpose i/o ports (open-drain): 8 ports total: 85 ports ?timer timebase timer/watchdog timer: 1 channel 8/16-bit ppg timers 0, 1: 8-bit 2 channels or 16-bit 1 channel ? 16-bit re-load timers 0, 1: 2 channels (continued) mb90520 series 3 (continued) ? 16-bit i/o timer 16-bit free-run timers 1, 2: 2 channels input captures 0, 1 (icu): generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. output compares 0, 1 (ocu): generates an interrupt request and reverses the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. 8/16-bit up/down counter/timers 0, 1: 1 channel (8-bit 2 channels) ? extended i/o serial interfaces 0, 1: 1 channel ?uart (sci) with full-duplex double buffer clock asynchronized or clock synchronized transmission can be selectively used. ? dtp/external interrupt circuit (8 channels) a module for starting extended intelligent i/o service (ei 2 os) and generating an external interrupt triggered by an external input. ? wake-up interrupt receives external interrupt requests and generates an interrupt request upon an l level input. ? delayed interrupt generation module generates an interrupt request for switching tasks. ? 8/10-bit a/d converter (8 channels) 8/10-bit resolution can be selectively used. starting by an external trigger input. conversion time: minimum 15.0 m s (at machine clock frequency of 16 mhz, including sampling time) ? 8-bit d/a converter (based on the r-2r system) 8-bit resolution: 2 channels (independent) setup time: 12.5 m s ? clock timer: 1 channel ? lcd controller/driver a common driver and a segment driver that can directly drive the lcd (liquid crystal display) panel ? clock output function note: do not set external bus mode for the mb90520 series because it cannot be operated in this mode. mb90520 series 4 n product lineup (continued) MB90522 mb90523 mb90f523 mb90v520 classification mask rom product flash rom product evaluation product rom size 64 kbytes 128 kbytes none ram size 4 kbytes 6 kbytes cpu functions number of instructions: 351 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1 bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock frequency of 16 mhz) interrupt processing time: 1.5 m s (at machine clock frequency of 16 mhz, minimum value) ports general-purpose i/o ports (cmos output): 53 general-purpose i/o ports (via pull-up resistor): 24 general-purpose i/o ports (n-ch open-drain output): 8 total: 85 uart (sci) clock synchronized transmission (62.5 kbps to 1 mbps) clock asynchronized transmission (1202 bps to 9615 bps) transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit a/d converter conversion precision: 8/10-bit can be selectively used. number of inputs: 8 one-shot conversion mode (converts selected channel only once) scan conversion mode (converts two or more successive channels and can program up to 8 channels.) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timers 0, 1 number of channels: 1 (8-bit 2 channels) ppg operation of 8-bit or 16-bit pulse wave of given intervals and given duty ratios can be output. pulse interval: 62.5 ns to 1 m s (at machine clock frequency of 16 mhz) 8/16-bit up/down counter/ timers 0, 1 number of channels: 1 (8-bit 2 channels) event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel 16-bit i/o timer 16-bit free-run timers 1, 2 number of channels: 2 overflow interrupts item part number mb90520 series 5 (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) assurance for the mb90v520 is given only for operation with a tool at a power voltage of 3.0 v to 5.5 v, an operating temperature of 0 to 55 degrees centigrade, and an operating frequency of 1 mhz to 16 mhz. part number mb90523 mb90523 mb90f523 mb90v520 item 16-bit i/o timer output compares 0, 1 (ocu) number of channels: 8 pin input factor: match signal of compare register input captures 0, 1 (icu) number of channels: 2 rewriting register value upon pin input (rising, falling, or both edges) dtp/external interrupt circuit number of inputs: 8 started by rising edge, falling edge, h level input, or l level input. external interrupt circuit or extended intelligent i/o service (ei 2 os) can be used. wake-up intrrupt number of inputs: 8 started by l level input. delayed interrupt generation module interrupt generation module for switching tasks used in real-time operating systems. extended i/o serial interfaces 0, 1 clock synchronized transmission (3125 bps to 1 mbps) lsb first/msb first timebase timer 18-bit counter interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 mhz) 8-bit d/a converter 8-bit resolution number of channels: 2 channels based on r-2r system lcd controller/driver number of common output pins: 4 number of segment output pins: 32 number of power supply pins for lcd drive: 4 ram for lcd indication: 16 bytes booster for lcd drive: internal split resistor for lcd drive: internal watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) low-power consumption (stand-by) mode sleep/stop/cpu intermittent operation/clock timer/hardware stand-by process cmos power supply voltage for operation* 3.0 v to 5.5 v 4.0 v to 5.5 v 3.0 v to 5.5 v mb90520 series 6 n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. n differences among products memory size in evaluation with an evaluation chip, note the difference between the evaluation chip and the chip actually used. the following items must be taken into consideration. ? the mb90v520 does not have an internal rom. however, operations equivalent to those performed by a chip with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by setting the development tool. ? in the mb90v520, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h are mapped to bank fe and ff only. (this setting can be changed by configuring the development tool.) ? in the MB90522, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h to bank ff only. ? in the mb90523/f523, images from ff4000 h to ffffff h are mapped to bank 00, and fe0000 h to ff3fff h to bank fe and bank ff. package MB90522 mb90523 mb90f523 fpt-120p-m05 fpt-120p-m13 mb90520 series 7 n pin assignment p30 v ss p27/adtg p26/zin0/int7 p25/bin0 p24/ain0 p23/ic11 p22/ic10 p21/ic01 p20/ic00 p17/wi7 p16/wi6 p15/wi5 p14/wi4 p13/wi3 p12/wi2 p11/wi1 p10/wi0 p07 p06/int6 p05/int5 p04/int4 p03/int3 p02/int2 p01/int1 p00/int0 v cc x1 x0 v ss pa6/seg14 pa7/seg15 v ss c p50/sin2/ain1 p51/sot2/bin1 p52/sck2/zin1 dv cc dv ss p53/da0 p54/da1 av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 v cc p70/ti0/out4 p71/to0/out5 p72/ti1/out6 p73/to1/out7 p74/com0 p75/com1 (top view) (fpt-120p-m05) (fpt-120p-m13) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p31/ckot p32/out0 p33/out1 p34/out2 p35/out3 p36/pg00 p37/pg01 v cc p40/pg10 p41/pg11 p42/sin0 p43/sot0 p44/sck0 p45/sin1 p46/sot1 p47/sck1 seg00 seg01 seg02 seg03 seg04 seg05 seg06 seg07 pa0/seg08 pa1/seg09 pa2/seg10 pa3/seg11 pa4/seg12 pa5/seg13 rst md0 md1 md2 hst v3 v2 v1 v0 p97/seg31 p96/seg30 p95/seg29 p94/seg28 p93/seg27 p92/seg26 p91/seg25 x0a x1a p90/seg24 p87/seg23 p86/seg22 p85/seg21 p84/seg20 p83/seg19 p82/seg18 p81/seg17 p80/seg16 v ss p77/com3 p76/com2 mb90520 series 8 n pin description pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 92, 93 x0, x1 a this is a high-speed crystal oscillator pin. 74, 73 x0a, x1a b this is a low-speed crystal oscillator pin. 89 to 87 md0 to md2 c this is an input pin for selecting operation modes. connect directly to v cc or v ss . 90 rst c this is an external reset request signal input pin. 86 hst c this is a hardware stand-by input pin. 95 to 101 p00 to p06 d this is a general-purpose i/o port. this function can be set by the port 0 input pull-up resistor setup register (rdr0) for input. for output, however, this function is invalid. int0 to int6 this is a request input pin of the dtp/external interrupt circuit ch.0 to ch.6. 102 p07 d this is a general-purpose i/o port. this function can be set by the port 0 input pull-up resistor setup register (rdr0) for input. for output, however, this function is invalid. 103 to 110 p10 to 17 d this is a general-purpose i/o port. this function can be set by the port 1 input pull-up resistor setup register (rdr1) for input. for output, however, this function is invalid. wi0 to wi7 this is an i/o pin for wake-up interrupts. 111, 112, 113, 114 p20, p21, p22, p23 e this is a general-purpose i/o port. ic00, ic01, ic10, ic11 this is a trigger input pin for input capture (icu) 0 and 1. since this input is used as required for input capture 0 and 1 (icu) ch.0, ch.01, ch.10 and ch.11 input operation, output by other functions must be suspended except for intentional operation. 115 p24 e this is a general-purpose i/o port. ain0 this port can be used as count clock a input for 8/16-bit up/down counter/timer 0. 116 p25 e this is a general-purpose i/o port. bin0 this port can be used as count clock b input for 8/16-bit up/down counter/timer 0. *1: fpt-120p-m05 *2: fpt-120p-m13 (continued) mb90520 series 9 pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 117 p26 e this is a general-purpose i/o port. zin0 this port can be used as count clock z input for 8/16-bit up/down counter/timer 0. int7 this is a request input pin of the dtp/external interrupt circuit ch.7. 118 p27 e this is a general-purpose i/o port. adtg this is an external trigger input pin of the 8/10-bit a/d converter. since this input is used as required for 8/10-bit a/d converter input operation, output by other functions must be suspended except for intentional operation. 120 p30 e this is a general-purpose i/o port. 1 p31 e this is a general-purpose i/o port. ckot this is a clock monitor function output pin. this function is valid when clock monitor output is enabled. 2 p32 e this is a general-purpose i/o port. this function becomes valid when waveform output from the out0 is disabled. out0 this is an event output pin for output compare 0 (ocu) ch.0. this function is valid when output for each channel is enabled. 3 p33 e this is a general-purpose i/o port. this function becomes valid when waveform output from the out1 is disabled. out1 this is an event output pin for output compare 0 (ocu) ch.1. this function is valid when output for each channel is enabled. 4 p34 e this is a general-purpose i/o port. this function becomes valid when waveform output from the out2 is disabled. out2 this is an event output pin for output compare 0 (ocu) ch.2. this function is valid when output for each channel is enabled. 5 p35 e this is a general-purpose i/o port. this function becomes valid when waveform output from the out3 is disabled. out3 this is an event output pin for output compare 0 (ocu) ch.3. this function is valid when output for each channel is enabled. 6 p36 e this is a general-purpose i/o port. this function becomes valid when waveform output from the pg00 is disabled. pg00 this is an output pin of 8/16-bit ppg timer 0. this function becomes valid when waveform output from pg00 is enabled. (continued) *1: fpt-120p-m05 *2: fpt-120p-m13 mb90520 series 10 pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 7 p37 e this is a general-purpose i/o port. this function becomes valid when waveform output from the pg01 is disabled. pg01 this is an output pin of 8/16-bit ppg timer 0. this function becomes valid when waveform output from pg01 is enabled. 9, 10 p40, p41 d this is a general-purpose i/o port. this function becomes valid when waveform output from the pg10 and pg11 are disabled. this function can be set by the pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. pg10, pg11 this is an output pin of 8/16-bit ppg timer 1. this function becomes valid when waveform outputs from pg10 and pg11 are enabled. 11 p42 d this is a general-purpose i/o port. this function can be set by the pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sin0 this is a serial data input pin of uart (sci). because this input is used as required when uart (sci) is performing input operations, it is necessary to stop outputs by other functions unless such outputs are made intentionally. when using other output functions as well, disable output during sin operation. 12 p43 d this is a general-purpose i/o port. this function can be set by the pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sot0 this is a serial data output pin of uart (sci). this function becomes valid when serial data output from uart (sci) is enabled. 13 p44 d this is a general-purpose i/o port. this function can be set by the pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sck0 this is a serial clock i/o pin of uart (sci). this function becomes valid when serial clock output from uart (sci) is enabled. 14 p45 d this is a general-purpose i/o port. this function can be set by the port 4 input pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sin1 this is a data input pin for extended i/o serial interface 0. since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. when using other output functions as well, disable output during sin operation. (continued) *1: fpt-120p-m05 *2: fpt-120p-m13 mb90520 series 11 pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 15 p46 d this is a general-purpose i/o port. this function can be set by the port 4 input pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sot1 this is a data output pin for extended i/o serial interface 0. this function becomes valid when serial data output from sot1 is enabled. 16 p47 d this is a general-purpose i/o port. this function can be set by the port 4 input pull-up resistor setup register (rdr4) for input. for output, however, this function is invalid. sck1 this is a serial clock i/o pin for extended i/o serial interface 0. this function becomes valid when serial clock output from sck1 is enabled. 35 p50 d this is a general-purpose i/o port. sin2 this is a data input pin for extended i/o serial interface 1. since this input is used as required for serial data input operation, output by other functions must be suspended except for intentional operation. ain1 this port can be used as count clock a input for 8/16-bit up/down counter/timer 1. 36 p51 d this is a general-purpose i/o port. sot2 this is a data output pin for extended i/o serial interface 1. this function becomes valid when serial data output from sot2 is enabled. bin1 this port can be used as count clock b input for 8/16-bit up/down counter/timer 1. 37 p52 d this is a general-purpose i/o port. sck2 this is a serial clock i/o pin for extended i/o serial interface 1. this function becomes valid when serial clock output from serial sck2 is enabled. zin1 this port can be used as control clock z input for 8/16-bit up/down counter/timer 1. 40, 41 p53, p54 i this is a general-purpose i/o port. da0, da1 these are analog signal output pins for 8-bit d/a converter ch.0 and ch.1. 46 to 53 p60 to p67 k this is a general-purpose i/o port. the input function become valid when the analog input enable register (ader) is set to select a port. an0 to an7 these are analog input pins of the 8/10-bit a/d converter. this function is valid when the analog input enable register (ader) is enabled. (continued) *1: fpt-120p-m05 *2: fpt-120p-m13 mb90520 series 12 pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 55, 57 p70, p72 e this is a general-purpose i/o port. ti0, ti1 these are event input pins for 16-bit re-load timers 0 and 1. since this input is used as required for 16-bit re-load timers 0 and 1 operation, output by other functions must be suspended except for intentional operation. out4, out6 these are event output pins for output compare 1 (ocu) ch.4 and ch.6. this function is valid when output for each channel is enabled. 56, 58 p71, p73 e this is a general-purpose i/o port. this function is valid when to0 and to1 output are disabled. to0, to1 these are output pins for 16-bit re-load timers 0 and 1. this function is valid when to0 and to1 output are enabled. out5, out7 these are event output pins for output compare 1 (ocu) ch.5 and ch.7. this function is valid when output for each channel is enabled. 59 to 62 p74 to p77 l this is a general-purpose i/o port. this function is valid with port output specified for the lcd controller/driver control register. com0 to com3 these are common pins for the lcd controller/driver. this function is valid with common output specified for the lcd controller/driver control register. 64 to 71 p80 to p87 l this is a general-purpose i/o port. this function is valid with port output specified for the lcd controller/driver control register. seg16 to seg23 these are segment outputs for the lcd controller/driver. this function is valid with segment output specified for the lcd controller/driver control register. 72, 75 to 81 p90, p91 to p97 m this is a general-purpose i/o port. the maximum i ol can be 10ma. this function is valid with port output specified for the lcd controller/driver control register. seg24, seg25 to seg31 these are segment outputs for the lcd controller/driver. this function is valid with port output specified for the lcd controller/driver control register. 17 to 24 seg00 to seg07 f these are pins dedicated to lcd segments 00 to 07 for the lcd controller/driver. 25 to 32 pa0 to pa7 l this is a general-purpose i/o port. this function is valid with port output specified for the lcd controller/driver control register. seg08 to seg15 these are pins for lcd segments 08 to 15 for the lcd controller/ driver. units of four ports or segments can be selected by the internal register in the lcd controller. (continued) *1: fpt-120p-m05 *2: fpt-120p-m13 mb90520 series 13 (continued) pin no. pin name circuit type function lqfp-120* 1 qfp-120* 2 34 c g this is a capacitance pin for power supply stabilization. connect an external ceramic capacitor rated at about 0.1 f. this capacitor is not, however, required for the m90f523 (flash product). 82 to 85 v0 to v3 n this is a pin for the reference power supply for the lcd controller/ driver. 8, 54, 94 v cc power supply this is a power supply (5.0 v) input pin to the digital circuit. 33, 63, 91, 119 v ss power supply this provides the gnd level (0.0 v) input pin for the digital circuit. 42 av cc h this is a power supply for the analog circuit. make sure to turn on/turn off this power supply with a voltage exceeding av cc applied to v cc . 43 avrh j this is a reference voltage input to the analog circuit. make sure to turn on/turn off this power supply with a voltage exceeding avrh applied to av cc . 44 avrl h this is a reference voltage input to the analog circuit. 45 av ss h this is a gnd level of the analog circuit. 38 dv cc h this is the vref input pin for the d/a converter. the voltage to be applied must not exceed v cc . 39 dv ss h this is the gnd level pin for the d/a converter. the potential must be the same as v ss. *1: fpt-120p-m05 *2: fpt-120p-m13 mb90520 series 14 n i/o circuit type (continued) type circuit remarks a ? high-speed oscillation feedback resistor approx. 1m w b ? low-speed oscillation feedback resistor approx. 1m w c ? hysteresis input d ? hysteresis input (can be set with the input pull-up resistor) cmos level output ? pull-up resistor approx. 50 k w ? provided with a standby control function for input interruption x1 x0 nch nch pch pch standby control signal x1a x0a nch pch pch nch standby control signal hysteresis input r r i ol = 4 ma pch pch nch hysteresis input selecting signal with or without a input pull-up resistor standby control for input interruption mb90520 series 15 (continued) type circuit remarks e ? cmos hysteresis input/output ? cmos level output ? provided with a standby control function for input interruption f ? pins dedicated to segment output g ? c pin output (pin for capacitor connection) n.c. pin for the mb90f523 h ? analog power input protector i ? cmos hysteresis input/output ? pin for analog output/cmos output (during analog output, cmos output is not produced.) (analog output has priority over cmos output: dae = 1) ? provided with a standby control function for input interruption i ol = 4 ma v cc r pch nch hysteresis input standby control for input interruption r pch nch pch nch avp pch nch r i ol = 4 ma dao v cc pch nch hysteresis input standby control for input interruption mb90520 series 16 type circuit remarks j ? input pin for ref+ power for the a/d converter provided with power protection k ? hysteresis input/analog input ? cmos output ? provided with a standby control for input interruption l ? cmos hysteresis input/output ? segment input ? standby control to cut off the input is available in segment input operation m ? hysteresis input ? nch open-drain output (high current for lcd drive) ? standby control to cut off the input is available in segment input operation n ? reference power supply pin for the lcd controller ane avr ane pch pch nch nch r i ol = 4 ma nch pch hysteresis input standby control for input interruption analog input i ol = 4 ma r nch pch hysteresis input seg standby control for input interruption i ol = 10 ma r nch nch hysteresis input standby control for input interruption r i ol = 10 ma nch pch mb90520 series 17 n handling devices 1. ensuring that the voltage does not exceed the maximum rating (to avoid a latch-up). in cmos ics, a latch-up phenomenon is caused when a voltage exceeding vcc or below vss is applied to input or output pins or if a voltage exceeding the rating is applied across vcc and vss. when a latch-up is caused, the power supply current may be dramatically increased, resulting in thermal breakdown of devices. to avoid the latch-up, make sure that the voltage does not exceed the maximum rating. in turning on/turning off the analog power supply, make sure the analog power voltages (avcc, avrh, dvcc) and analog input voltages do not exceed the digital voltage (v cc ). and also make sure the voltages applied to the lcd power supply pins (v3 to v0) do not exceed the power supply voltage (v cc ). 2. handling unused pins ? unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. unused input pins should be pulled-up or pull-down through at least 2 k w resistance. ? unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. 3. notes on using external clock in using the external clock, drive x0 pin only and leave x1 pin unconnected. 4. unused sub clock mode if sub clock modes are not used, the oscillator should be connected to the x0a pin and x1a pin. 5. power supply pins in products with multiple v cc or v ss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-ups. however, the pins should be connected to external powers and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via lowest impedance to power lines. it is recommended that a bypass capacitor of around 0.1 m f be placed between the v cc and v ss pins near the device. ? using external clock x0 x1 open mb90520 series mb90520 series 18 6. crystal oscillator circuit noise around the x0 and x1 pins may cause abnormal operation in this device. in designing printed circuit boards, the x0 and x1 pins and crystal oscillator (or ceramic oscillator), as well as the bypass capacitor to the ground, should be placed as close as possible, and the related wiring should have as few crossings with other wiring as possible. circuit board artwork in which the area of the x0 and x1 pins is surrounded by grounding is recommended for stabilizing the operation. 7. turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply, d/a converter power supply (av cc , avrh, avrl, dv cc , dv ss ) and analog inputs (an0 to an7) after turning on the digital power supply (v cc ). turn off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that avrh and dv cc do not exceed av cc (turning on/off the analog and digital supplies simultaneously is acceptable). 8. connection of unused pins of a/d converter connect unused pins of a/d converter and those of d/a converter to av cc = dv cc = v cc , av ss = avrh = avrl = v ss . 9. n.c. pin the n.c. (internally connected) pin must be opened for use. 10.notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 m s or more (0.2 v to 2.7 v). 11.use of seg/com pins for the lcd controller/driver as ports in mb90520 series, pins seg08 to seg31, and com0 to com3 can also be used as general-purpose ports. the electrical standard is such that pins seg08 to seg23, and com0 to com3 have the same ratings as the cmos output port, while pins seg24 to seg31 have the same ratings as the open-drain type. ? using power supply pins v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90520 series mb90520 series 19 12. indeterminate outputs from ports 0 and 1 the outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. pay attention to the port output timing shown as follow 13.initialization the device contains internal registers that can be initialized only by a power-on reset. to initialize the internal registers, restart the power supply. 14. interrupt recovery from standby if an external interrupt is used for recovery from standby, use an h level input request. an l level request causes abnormal operation. 15.precautions for use of div a, ri , and divw a, ri instructions the signed multiplication-division instructions div a, ri, and divw a, rwi should be used when the corresponding bank registers (dtb, adb, usb, ssb) are set to value 00h. if the corresponding bank registers (dtb, adb, usb, ssb) are set to a value other than 00h, then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 16. precautions for use of realos extended intelligent i/o service(ei 2 os) cannot be used, when realos is used. oscillation setting time *2 step-down circuit setting time *1 vcc(power-supply pin) ponr(power-on reset) signal rst (external asynchronous reset) signal rst(internal reset) signal oscillation clock signal ka(internal operation clock a) signal kb(internal operation clock b) signal port(port output)signal indereterminate period * : 1:step-down circuit setting time : 2 17 /oscillation clock frequency (oscillation clock frequency of 16 mhz: 8.19 ms) * : 2:oscillation setting time: 2 18 /oscillation clock frequency (oscillation cllock frequency of 16 mhz: 16.38 ms) ? timming chart of indeterminate outputs from ports o and 1 mb90520 series 20 n block diagram f 2 mc-16lx cpu x0, x1 x0a, x1a rst hst p45/sin1 p46/sot1 p47/sck1 p07 p24/ain0 p25/bin0 p26/zin0/int7 p00/int0 to p06/int6 p20/ic00 p21/ic01 p32/out0 p33/out1 p34/out2 p35/out3 p31/ckot p30 p36/pg00 p37/pg01 p40/pg10 p41/pg11 p42/sin0 p43/sot0 p44/sck0 p10/wi0 to p17/wi7 p80/seg16 to p87/seg23 p90/seg24 to p97/seg31 pa0/seg08 to pa7/seg15 seg00 to seg07 v0 to v3 p74/com0 to p77/com3 dv cc dv ss p70/ti0/out4 p71/to0/out5 p72/ti1/out6 p73/to1/out7 p22/ic10 p23/ic11 p60/an0 to p67/an7 av cc av ss avrh avrl p27/adtg p50/sin2/ain1 p51/sot2/bin1 p52/sck2/zin1 p53/da0 p54/da1 clock control block* 1 (including timebase timer) oscillation clock sub clock port 0* 2 dtp/ external interrupt circuit 77 24 8 8 8 8 4 4 4 port 8* 5 , 9* 5 , a* 5 lcd controller/ driver port 7* 4 16-bit re-load timer 0 16-bit re-load timer 1 port 2* 4 3 8/16-bit up/down counter/timer 0, 1 output compare (ocu) 16-bit i/o timer 2 4 16-bit free-run timer 2 2 input capture 1 (icu) port 2* 4 port 6* 4 88 8/10-bit a/d converter port 2* 4 interrupt controller port 5* 5 sio ch.1 2 8-bit d/a converter 2 ch. ram rom input capture 0 (icu) 16-bit i/o timer 1 2 16-bit free-run timer 1 4 output compare 0 (ocu) clock output port 3* 4 2 2 8/16-bit ppg timer 0, 1 uart (sci) sio ch.0 port 4* 2 port 1* 2 8 8 wake-up interrupt notes: actually 16-bit free-run timer 1 is supported although two free-run timers are seemingly supported. *1: the clock control circuit comprises a watchdog timer, a timebase timer, and a power consumption controller. *2: a register for setting a pull-up resistor is supported. *3: this is a high-current port for an lcd drive. *4: a register for setting a pull-up resistor is supported. signals in the cmos level are input and output. *5: also used for lcd output. with this port used as is, nch open-drain output develops. a register for setting a pull-up resi stor is supported. intrnal data bus md0 to md2, c, v cc , v ss other pins mb90520 series 21 n memory map note: the rom data of bank ff is reflected in the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit of bank ff and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the rom without stating far. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are actually accessed. since the rom area of the ff bank exceeds 48k bytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff4000 h to ffffff h looks, therefore, as if it were the image for 00400 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff4000 h to ffffff h . part number address #1* address #2 * address #3 * MB90522 ff0000 h 004000 h 001100 h mb90523 fe0000 h 004000 h 001100 h mb90f523 fe0000 h 004000 h 001100 h ffffff h address #1 fe0000 h 010000 h address #2 address #3 000100 h 0000c0 h 000000 h rom area rom area (image of bank ff) ram register peripheral : internal access memory : access prohibited *: addresses #1, #2 and #3 vary with product type. 002000 h 004000 h single chip mode a mirroring function is supported. mb90520 series 22 n f 2 mc-16lx cpu programming model ? dedicated registers : accumlator (a) dual 16-bit register used for storing results of calculation, etc. the two 16-bit registers can be combined to be used as a 32-bit register. : additional data bank register (adb) 8-bit register for displaying the additional data space. : user stack pointer (usp) 16-bit pointer for containing a user stack address. : user stack bank register (usb) 8-bit register for displaying the user stack space. : system stack pointer (ssp) 16-bit pointer for displaying the status of the system stack address. : processor status (ps) 16-bit register for displaying the system status. : program bank register (pcb) 8-bit register for displaying the program space. : data bank register (dtb) 8-bit register for displaying the data space. : program counter (pc) 16-bit register for displaying the storing location of the current instruction code. : direct page register (dpr) 8-bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode. : system stack bank register (ssb) 8-bit register for displaying the system stack space. ah al usp ssp dpr pcb dtb usb ssb adb ps pc 8-bit 16-bit 32-bit mb90520 series 23 ? general-purpose registers ? processor status (ps) maximum of 32 banks 000180 h + (rp 10 h ) r7 r5 r3 r1 r6 r4 r2 r0 rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 rw3 rw2 rw1 rw0 16-bit ilm rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ilm2 b4 ilm1 ilm0 b3 b2 b1 b0 i s t n z v c 00 000 0 00 1 0xxx x x ps initial value x : indeterminate : unused mb90520 series 24 n i/o map (continued) address abbreviated register name register name read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 x x x x x x x x b 000001 h pdr1 port 1 data register r/w port 1 x x x x x x x x b 000002 h pdr2 port 2 data register r/w port 2 x x x x x x x x b 000003 h pdr3 port 3 data register r/w port 3 x x x x x x x x b 000004 h pdr4 port 4 data register r/w port 4 x x x x x x x x b 000005 h pdr5 port 5 data register r/w port 5 x x x x x x x x b 000006 h pdr6 port 6 data register r/w port 6 x x x x x x x x b 000007 h pdr7 port 7 data register r/w port 7 x x x x x x x x b 000008 h pdr8 port 8 data register r/w port 8 x x x x x x x x b 000009 h pdr9 port 9 data register r/w port 9 x x x x x x x x b 00000a h pdra port a data register r/w port a x x x x x x x x b 00000b h lcdcmr port 7/com pin selection register r/w port 7, lcd controller/driver xxxx0 0 0 0 b 00000c h ocp4 ocu compare register ch.4 r/w 16-bit i/o timer (output compare 1 (ocu) section) xxxxxxxx b 00000d h xxxxxxxx b 00000e h (disabled) 00000f h eifr wake-up interrupt flag register r/w wake-up interrupt xxxxxxx0 b 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 x x x 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 0 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 0 0 0 0 0 0 0 0 b 00001a h ddra port a direction register r/w port a 0 0 0 0 0 0 0 0 b 00001b h ader analog input enable register r/w port 6, a/dconverter 11111111 b 00001c h ocp5 ocu compare register ch.5 r/w 16-bit i/o timer (output compare 1 (ocu) section) xxxxxxxx b 00001d h xxxxxxxx b 00001e h (disabled) 00001f h eicr wake-up interrupt enable register w wake-up interrupt 00000000 b mb90520 series 25 (continued) address abbreviated register name register name read/ write resource name initial value 000020 h smr serial mode register r/w uart (sci) 00000000 b 000021 h scr serial control register r/w or w 00000100 b 000022 h sidr/ sodr serial input data register/ serial output data register r w xxxxxxxx b 000023 h ssr serial status register r/w or r 00001x00 b 000024 h smcsl0 serial mode control lower status register 0 r/w extended i/o serial interface 0 xxxx0 0 0 0 b 000025 h smcsh0 serial mode control upper status register 0 r/w 0 0 0 0 0 0 1 0 b 000026 h sdr0 serial data register 0 r/w xxxxxxxx b 000027 h cdcr communications prescaler control register r/w communica- tions prescaler control register 0xxx1111 b 000028 h smcsl1 serial mode control lower status register 1 r/w extended i/o serial interface 1 xxxx0 0 0 0 b 000029 h smcsh1 serial mode control upper status register 1 r/w 0 0 0 0 0 0 1 0 b 00002a h sdr1 serial data register 1 r/w xxxxxxxx b 00002b h (disabled) 00002c h ocs45 ocu control status register ch.45 r/w 16-bit i/o timer (output com- pare 1 (ocu) section) 0000xx00 b 00002d h xxx0 0 0 0 0 b 00002e h ocs67 ocu control status register ch.67 r/w 0000xx00 b 00002f h xxx0 0 0 0 0 b 000030 h enir dtp/interrupt enable register r/w dtp/external interrupt circuit 00000000 b 000031 h eirr dtp/interrupt factor register r/w x x x x x x x x b 000032 h elvr request level setting register r/w 00000000 b 000033 h 00000000 b 000034 h ocp6 ocu compare register ch.6 r/w 16-bit i/o timer (output com- pare 1 (ocu) section) xxxxxxxx b 000035 h xxxxxxxx b 000036 h adcs1 a/d control status register lower digits r/w 8/10-bit a/d converter 00000000 b 000037 h adcs2 a/d control status register upper digits r/w 0 0 0 0 0 0 0 0 b 000038 h adcr1 a/d data register lower digits r x x x x x x x x b 000039 h adcr2 a/d data register upper digits r or w 0 0 0 0 1 x x x b 00003a h dadr0 d/a converter data register ch.0 r/w 8-bit d/a converter xxxxxxxx b 00003b h dadr1 d/a converter data register ch.1 r/w x x x x x x x x b 00003c h dacr0 d/a control register 0 r/w xxxxxxx0 b 00003d h dacr1 d/a control register 1 r/w xxxxxxx0 b 00003e h clkr clock output enable register r/w clock monitor function xxxx0 0 0 0 b mb90520 series 26 (continued) address abbreviated register name register name read/ write resource name initial value 00003f h (disabled) 000040 h prll0 ppg0 re-load register l r/w 8/16-bit ppg timer 0, 1 xxxxxxxx b 000041 h prlh0 ppg0 re-load register h r/w x x x x x x x x b 000042 h prll1 ppg1 re-load register l r/w x x x x x x x x b 000043 h prlh1 ppg1 re-load register h r/w x x x x x x x x b 000044 h ppgc0 ppg0 operating mode control register r/w 0 x 0 0 0 x x 1 b 000045 h ppgc1 ppg1 operating mode control register r/w 0 x 0 0 0 0 0 1 b 000046 h ppgoe0/ ppgoe1 ppg0 and 1 output control registers r/w 0 0 0 0 0 0 0 0 b 000047 h (disabled) 000048 h tmcsr0 timer control status register lower ch.0 r/w 16-bit re-load timer 0 00000000 b 000049 h timer control status register upper ch.0 x x x x 0 0 0 0 b 00004a h tmr0/ tmrlr0 16-bit timer register upper, lower ch.0/ 16-bit re-load register upper, lower ch.0 r/w xxxxxxxx b 00004b h xxxxxxxx b 00004c h tmcsr1 timer control status register lower ch.1 r/w 16-bit re-load timer 1 00000000 b 00004d h timer control status register upper ch.1 x x x x 0 0 0 0 b 00004e h tmr1/ tmrlr1 16-bit timer register upper, lower ch.1/ 16-bit re-load register upper, lower ch.1 r/w xxxxxxxx b 00004f h xxxxxxxx b 000050 h ipcp0 icu data register ch.0 r 16-bit i/o timer (input compare 0, 1 (icu) section) xxxxxxxx b 000051 h xxxxxxxx b 000052 h ipcp1 icu data register ch.1 r xxxxxxxx b 000053 h xxxxxxxx b 000054 h ics01 icu control status register r/w 0 0 0 0 0 0 0 0 b 000055 h (disabled) 000056 h tcdt1 free-run timer data register 1 r/w 16-bit i/o timer (16-bit free-run timer 1 section) 00000000 b 000057 h 00000000 b 000058 h tccs1 free-run timer control status register 1 r/w 00000000 b 000059 h (disabled) 00005a h ocp0 ocu compare register ch.0 r/w 16-bit i/o timer (output compare 0 (ocu) section) xxxxxxxx b 00005b h xxxxxxxx b 00005c h ocp1 ocu compare register ch.1 r/w xxxxxxxx b 00005d h xxxxxxxx b 00005e h ocp2 ocu compare register ch.2 r/w xxxxxxxx b 00005f h xxxxxxxx b 000060 h ocp3 ocu compare register ch.3 r/w xxxxxxxx b 000061 h xxxxxxxx b mb90520 series 27 (continued) address abbreviated register name register name read/ write resource name initial value 000062 h ocs01 ocu control status register ch.01 r/w 16-bit i/o timer (output compare 0 (ocu) section) 0000xx00 b 000063 h xxx00000 b 000064 h ocs23 ocu control status register ch.23 r/w 0000xx00 b 000065 h xxx00000 b 000066 h tcdt2 free-run timer data register 2 r/w 16-bit i/o timer (16-bit free-run timer 2 section) 00000000 b 000067 h 00000000 b 000068 h tccs2 free-run timer control status register 2 r/w 00000000 b 000069 h (disabled) 00006a h lcr0 lcdc control registers 0 and 1 r/w lcd controller/ driver 00010000 b 00006b h lcr1 r/w 00000000 b 00006c h ocp7 ocu compare register ch.7 r/w 16-bit i/o timer (output compare 1 (ocu) section) xxxxxxxx b 00006d h xxxxxxxx b 00006e h (disabled) 00006f h romm rom mirroring function selection register w rom mirroring function selection module xxxxxxx1 b 000070 h to 00007f h vram ram for lcd indication r/w lcd controller/ driver xxxxxxxx b 000080 h udcr0 up/down count register 0 r 8/16-bit up/down counter/timer 0, 1 00000000 b 000081 h udcr1 up/down count register 1 r 0 0 0 0 0 0 0 0 b 000082 h rcr0 re-load compare register 0 w 0 0 0 0 0 0 0 0 b 000083 h rcr1 re-load compare register 1 w 0 0 0 0 0 0 0 0 b 000084 h csr0 counter status register 0 r/w 00000000 b 000085 h (reserved area)* 3 000086 h ccrl0 counter control register 0 r/w 8/16-bit up/down counter/timer 0, 1 x0000000 b 000087 h ccrh0 00000000 b 000088 h csr1 counter status register 1 r/w 00000000 b 000089 h (reserved area)* 3 00008a h ccrl1 counter control register 1 r/w 8/16-bit up/down counter/timer 0, 1 x0000000 b 00008b h ccrh1 x0000000 b 00008c h rdr0 port 0 input pull-up resistor setup register r/w port 0 00000000 b 00008d h rdr1 port 1 input pull-up resistor setup register r/w port 1 00000000 b 00008e h rdr4 port 4 input pull-up resistor setup register r/w port 4 00000000 b mb90520 series 28 (continued) address abbreviated register name register name read/ write resource name initial value 00008f h to 00009d h (area used by the system)* 3 00009e h pacsr program address detection control status register r/w address match detection function 00000000 b 00009f h dirr delayed interrupt factor generation/ cancellation register r/w delayed inter- rupt generation module xxxxxxx0 b 0000a0 h lpmcr low-power consumption mode control register r/w or w low-power consumption (stand-by) mode 00011000 b 0000a1 h ckscr clock select register r/w or r 11111100 b 0000a2 h to 0000a7 h (disabled) 0000a8 h wdtc watchdog timer control register r or w watchdog timer x x x x x x x x b 0000a9 h tbtc timebase timer control register r/w timebase timer 1 x x 0 0 0 0 0 b 0000aa h wtc clock timer control register r/w or r clock timer 1x001000 b 0000ab h to 0000ad h (disabled) 0000ae h fmcs flash control register r/w flash interface 1 x x 0 0 1 0 0 b 0000af h (disabled) 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b mb90520 series 29 (continued) descriptions for read/write r/w: readable and writable r: read only w: write only descriptions for initial value 0 : the initial value is 0. 1 : the initial value is 1. x : the initial value is indeterminate. *1: this area is the only external access area having an address of 0000ff h or lower. an access operation to this area is handled as that to external i/o area. *2: for details of the ram area, see the memory map. *3: the reserved area is basically disabled because it is used in the system. *4: area used by the system is the area set by the resistor for evaluating tool. notes: ? for bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value. note that the values are different from reading results. for lpmcr/ckscr/wdtc, there are cases in which initialization is performed or not performed, depending on the types of the reset. the value listed is the initial value in cases where initialization is per formed. ? the addresses following 0000ff h are reserved. no external bus access signal is generated. ? boundary #### h between the ram area and the reserved area varies with the product models. ? channels 0 to 3 of the ocu compare register use 16-bit free-run timer 2, while channels 4 to 7 of the ocu compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (icu) 0 and 1. address abbreviated register name register name read/ write resource name initial value 0000be h icr14 interrupt control register 14 r/w interrupt controller 00000111 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h to 0000ff h (external area)* 1 000100 h to 00#### h (ram area)* 2 00#### h to 001fef h (reserved area)* 3 001ff0 h padr0 program address detection register 0 r/w address match detection function xxxxxxxx b 001ff1 h program address detection register 1 r/w x x x x x x x x b 001ff2 h program address detection register 2 r/w x x x x x x x x b 001ff3 h padr1 program address detection register 3 r/w x x x x x x x x b 001ff4 h program address detection register 4 r/w x x x x x x x x b 001ff5 h program address detection register 5 r/w x x x x x x x x b 001ff6 h to 001fff h (reserved area)* 3 mb90520 series 30 n interrupt factors, interrupt vectors, interrupt control registers (continued) interrupt source ei 2 os support interrupt vector interrupt control register priority number address icr address reset # 08 ffffdc h high int9 instruction # 09 ffffd8 h exception # 10 ffffd4 h 8/10-bit a/d converter # 11 ffffd0 h icr00 0000b0 h timebase timer # 12 ffffcc h dtp0/dtp1 (external interrupt 0/ external interrupt 1) # 13 ffffc8 h icr01 0000b1 h 16-bit free-run timer 1 overflow # 14 ffffc4 h extended i/o serial interface 0 # 15 ffffc0 h icr02 0000b2 h wake-up interrupt # 16 ffffbc h extended i/o serial interface 1 # 17 ffffb8 h icr03 0000b3 h dtp2/dtp3 (external interrupt 2/ external interrupt 3) # 18 ffffb4 h 8/16-bit ppg timer 0 counter borrow # 19 ffffb0 h icr04 0000b4 h dtp4/dtp5 (external interrupt 4/ external interrupt 5) # 20 ffffac h 8/16-bit up/down counter/timer 0 compare match # 21 ffffa0 h icr05 0000b5 h 8/16-bit up/down counter/timer 0 overflow up/down inversion # 22 ffffa4 h 8/16-bit ppg timer 1 counter borrow # 23 ffffa0 h icr06 0000b6 h dtp6/dtp7 (external interrupt 6/ external interrupt 7) # 24 ffff9c h output compare 1 (ocu) ch.4/ch.5 match # 25 ffff98 h icr07 0000b7 h clock prescaler # 26 ffff94 h output compare 1 (ocu) ch.6/ch.7 match # 27 ffff90 h icr08 0000b8 h 16-bit free-run timer 2 overflow # 28 ffff8c h 8/16-bit up/down counter/timer 1 compare match # 29 ffff88 h icr09 0000b9 h 8/16-bit up/down counter/timer 1 overflow, up/down inversion # 30 ffff84 h input capture 0 (icu) include # 31 ffff80 h icr10 0000ba h input capture 1 (icu) include # 32 ffff7c h low mb90520 series 31 (continued) : can be used : can not be used : can be used with ei 2 os stop function interrupt source ei 2 os support interrupt vector interrupt control register priority number address icr address output compare 0 (ocu) ch.0 match # 33 ffff78 h icr11 0000bb h high output compare 0 (ocu) ch.1 match # 34 ffff74 h output compare 0 (ocu) ch.2 match # 35 ffff70 h icr12 0000bc h output compare 0 (ocu) ch.3 match # 36 ffff6c h uart (sci) reception complete # 37 ffff68 h icr13 0000bd h 16-bit re-load timer 0 # 38 ffff64 h uart (sci) transmission complete # 39 ffff60 h icr14 0000be h 16-bit re-load timer 1 # 40 ffff5c h reserved # 41 ffff58 h icr15 0000bf h delayed interrupt generation module # 42 ffff54 h low mb90520 series 32 n peripherals 1. i/o port (1) input/output port port 0 through a are general-purpose i/o ports having a combined function as a resource input. the i/o ports can be used as general-purpose i/o ports only in the single-chip mode. ? operation as output port the pin is configured as an output port by setting the corresponding bit of the ddr register to 1. writing data to pdr register when the port is configured as output, the data is retained in the output latch in the pdr and directly output to the pin. the value of the pin (the same value retained in the output latch of pdr) can be read out by reading the pdr register. note: when a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the ddr register for output. however, values of bits configured as inputs by the ddr register are changed because input values to the pins are written into the output latch. to avoid this situation, configure the pins by the ddr register as output after writing output data to the pdr register when switching the bit used as input to output. ? operation as input port the pin is configured as input by setting the corresponding bit of the ddr register to 0. when the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance status. when data is written into the pdr register, the data is retained in the output latch of the pdr, but pin outputs are unaffected. reading the pdr register reads out the pin level (0 or 1). mb90520 series 33 (2) register configuration (continued) ? port 0 data register (pdr0) ? port 1 data register (pdr1) address 000000 h p07 p06 p05 p04 p03 p02 p01 p00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w address 000001 h initial value xxxxxxxx b initial value p17 p16 p15 p14 p13 p12 p11 p10 ? port 2 data register (pdr2) ? port 3 data register (pdr3) address 000002 h p27 p26 p25 p24 p23 p22 p21 p20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w address 000003 h initial value xxxxxxxx b initial value p37 p36 p35 p34 p33 p32 p31 p30 ? port 4 data register (pdr4) ? port 5 data register (pdr5) address 000004 h p47 p46 p45 p44 p43 p42 p41 p40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w address 000005 h initial value xxxxxxxx b initial value p54 p53 p52 p51 p50 ? port 6 data register (pdr6) ? port 7 data register (pdr7) address 000006 h p67 p66 p65 p64 p63 p62 p61 p60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w address 000007 h initial value xxxxxxxx b initial value p77 p76 p75 p74 p73 p72 p71 p70 ? port 8 data register (pdr8) address 000008 h p87 p86 p85 p84 p83 p82 p81 p80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b initial value ? port 9 data register (pdr9) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b initial value p97 p96 p95 p94 p93 p92 p91 p90 address 000009 h mb90520 series 34 (continued) ? port a data register (pdra) address 00000a h pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w xxxxxxxx b initial value ? port 0 direction register (ddr0) address 000010 h d07 d06 d05 d04 d03 d02 d01 d00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? port 2 direction register (ddr2) address 000012 h d27 d26 d25 d24 d23 d22 d21 d20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? port 4 direction register (ddr4) address 000014 h d47 d46 d45 d44 d43 d42 d41 d40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? port 1 direction register (ddr1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value d17 d16 d15 d14 d13 d12 d11 d10 ? port 3 direction register (ddr3) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w 00000000 b initial value d37 d36 d35 d34 d33 d32 d31 d30 address 000011 h address 000013 h ? port 6 direction register (ddr6) ? port 5 direction register (ddr5) address 000016 h d67 d66 d65 d64 d63 d62 d61 d60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxx00000 b initial value d54 d53 d52 d51 d50 address 000015 h ? port 7 direction register (ddr7) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value d77 d76 d75 d74 d73 d72 d71 d70 address 000017 h ? port 8 direction register (ddr8) address 000018 h d87 d86 d85 d84 d83 d82 d81 d80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value mb90520 series 35 (continued) ? port 0 input pull-up resistor setup register (rdr0) address 00008c h rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? port 9 direction register (ddr9) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value d97 d96 d95 d94 d93 d92 d91 d90 address 000019 h ? port a direction register (ddra) address 00001a h da7 da6 da5 da4 da3 da2 da1 da0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? port 4 input pull-up resistor setup register (rdr4) ? port 1 input pull-up resistor setup register (rdr1) address 00008e h rd47 rd46 rd45 rd44 rd43 rd42 rd41 rd40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b initial value rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 address 00008d h ? analog input enable register (ader) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w 11111111 b initial value ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 address 00001b h r/w : readable and writable x : indeterminate : undefined bits (read value undefined) ? port 7/com pin selection register (lcdcmr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w xxxx0000 b initial value com3 com2 com1 com0 address 00000b h mb90520 series 36 (3) block diagram ? input/output port pdr (port data register) ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1, or hardware standby mode standby control (spl=1) pch nch pin ? input pull-up resistor setup register (rdr) to resource input ddr (port direction register) pdr read pdr write ddr write ddr read direction latch output latch internal data bus standby control: stop, timebase timer mode and spl=1 standby control (spl=1) pch nch pin rdr (input pull-up resistor setup register) rdr write rdr read rdr latch pdr (port data register) pull-up resistor about 50 k w (5.0 v) pch mb90520 series 37 ? analog input enable register (ader) pdr (port data register) ader read ader write pdr write pdr read ader latch internal data bus standby control (spl=1) pch nch pin ddr write ddr read direction latch ader (analog input enable register) to analog input output latch rmw (read-modify-write type instruction) standby control: stop, timebase timer mode and spl=1 ddr (port direction register) mb90520 series 38 2. timebase timer the timebase timer is a 18-bit free-run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types : 2 12 /hclk, 2 14 /hclk, 2 16 /hclk, and 2 19 /hclk. the timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer, etc. (1) register configuration (2) block diagram ? timebase timer control register (tbtc) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w address 0000a9 h tbie tbof tbr tbc1 tbc0 1xx00000 b initial value r/w: readable and writable : undefined bits (read value undefined) reserved . . . . . . to 8/16-bit ppg timer timebase timer counter divided-by-2 of hclk power-on reset start stop-mode ckscr : mcs = 1 ? 0* 1 counter clear circuit interval timer selector clear tbof set tbof timebase timer control register (tbtc) timebase timer interrupt signal #12* 2 of : overflow hclk : oscillation clock frequency switch machine clock from oscillation clock to pll clock interrupt number *1: *2: reserved tbie tbr tbof tbc1 tbc0 to oscillation stabilization time selector of clock control block to watchdog timer of of of of 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 mb90520 series 39 3. watchdog timer the watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the cpu when the counter is not cleared for a preset period of time. (1) register configuration (2) block diagram ? watchdog timer control register (wdtc) address 0000a8 h ponr stbr wrst erst srst wte wt1 wt0 r : read only w: write only x : indeterminate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrr rwww initial value xxxxxxxx b hclk : oscillation clock frequency ponr stbr wrst erst srst wte wt1 wt0 watchdog timer control register (wdtc) start sleep-mode clr and start watchdog timer overflow to internal reset generation circuit counter clear control circuit count clock selector 2-bit counter watchdog timer reset generation circuit clear divided-by-2 of hclk (timebase timer counter) 2 1 2 2 ... 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 clr 2 4 clr start stop-mode start hold status mb90520 series 40 4. 8/16-bit ppg timer 0, 1 the 8/16-bit ppg timer is a 2-ch re-load timer module for outputting pulse having given frequencies/duty ratios. the two modules perform the following operation by combining functions. ? 8-bit ppg timer output 2-ch independent output mode this is a mode for operating independent 2-ch 8-bit ppg timers, in which pg00 and pg10 pins correspond to outputs from ppg0 and ppg1 respectively. ? 16-bit ppg timer output operation mode in this mode, ppg0 and ppg1 are combined to be operated as a 1-ch 8/16-bit ppg timer 0 and 1 operating as a 16-bit timer. because outputs during 16-bit ppg timer output operation mode are reversed by an underflow from ppg1, the same output pulses are output from pg10 and pg11 pins. ? 8 + 8-bit ppg timer output operation mode in this mode, ppg0 is operated as an 8-bit prescaler register, in which an underflow output of ppg0 is used as a clock source for ppg1. a prescaler output of ppg0 is output from pg00 and pg01 pins. ppg output of ppg1 is output from pg10 and pg11 pins. ? ppg output operation a pulse wave with any period/duty ratio is output. the module can also be used as a d/a converter with an external add-on circuit. mb90520 series 41 (1) register configuration ? ppg0 output control register (ppgoe0) ? ppg1 output control register (ppgoe1) ? ppg0 re-load register h (prlh0) address 000046 h pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w address 000046 h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w:readable and writable x : indeterminate : undefined bits (read value undefined) 00000000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w address 000041 h ? ppg1 re-load register h (prlh1) address 000043 h ? ppg0 re-load register l (prll0) ? ppg1 re-load register l (prll1) address 000040 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w address 000042 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b initial value xxxxxxxx b initial value xxxxxxxx b initial value xxxxxxxx b initial value xxxxxxxx b initial value ? ppg0 operating mode control register (ppgc0) address 000044 h pen0 pe00 pie0 puf0 0x000xx1 b initial value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w address 000045 h 0x000001 b initial value pen1 pe10 pie1 puf1 md1 md0 reserved ? ppg1 operating mode control register (ppgc1) reserved mb90520 series 42 (2) block diagram ? block diagram of 8/16-bit ppg timer 0 prlh0 timebase timer output (512/hclk) pen0 data bus for h digits pe00 pie0 puf0 data bus for l digits ppg0 operating mode control register (ppgc0) ppg0 re-load register prll0 temporary buffer (prlbh0) re-load selector l/h selector down counter (pcnt0) count value clear clk 2 select signal re-load underflow pulse selector ppg0 output latch reverse ppg output control circuit oprating mode control signal pin p36/pg00 count clock selector ppg1 underflow ppg0 underflow (to ppg1) select signal * : interrupt number hclk : oscillation clock frequency f : machine clock frequency r sq interrupt request #19* peripheral clock (16/ f ) peripheral clock (8/ f ) peripheral clock (4/ f ) peripheral clock (2/ f ) peripheral clock (1/ f ) pin p37/pg01 3 pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 ppg0, 1 output control register (ppgoe0,1) reserved mb90520 series 43 ? block diagram of 8/16-bit ppg timer 1 ppg1 underflow (to ppg0) * : interrupt number hclk : oscillation clock frequency f : machine clock frequency prlh0 pen1 data bus for h digits data bus for l digits ppg1 operating mode control register (ppgc1) prll0 temporary buffer (prlbh1) re-load selector (l/h selector) down counter (pcnt1) ppg1 output latch pin count value clear 2 select signal re-load underflow reverse ppg output control circuit p40/pg10 count clock selector select signal ppg1 re-load register operating mode control signal ppg0 underflow clk md0 interrupt request #23* timebase timer output (512/hclk) pei0 pie1 puf1 md1 md0 reserved r sq pin p41/pg11 pcs2 3 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 ppg0, 1 output control register (ppgoe0, 1) peripheral clock (16/ f ) peripheral clock (8/ f ) peripheral clock (4/ f ) peripheral clock (2/ f ) peripheral clock (1/ f ) mb90520 series 44 5. 16-bit re-load timer 0, 1 (with an event count function) the 16-bit re-load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external bus pin. either of the two functions can be selectively used. for this timer, an underflow is defined as the timing of transition from the counter value of 0000 h to ffff h . according to this definition, an underflow occurs after a counter value of [re-load register setting value + 1] . in operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelligent i/o service (ei 2 os). the mb90520 series has 2 channels of 16-bit re-load timers. (1) register configuration mod0 oute outl reld inte uf cnte trg ? timer control status register lower digits ch.0, ch.1 (tmcsr0, tmcsr1 : l) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value ? timer control status register upper digits ch.0, ch.1 (tmcsr0, tmcsr1 : h) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/wr/wr/wr/w xxxx 0000 b initial value csl1 csl0 mod2 mod1 tmcsr0 : 000049 h tmcsr1 : 00004d h ? 16-bit timer register upper and lower digits ch.0, ch.1 (tmr0, tmr1) xxxxxxxx b initial value bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrrrrrrrrrrrrrr xxxxxxxx b xxxxxxxx b xxxxxxxx b address tmcsr0 : 000048 h tmcsr1 : 00004c h address tmr0 : 00004b h 00004a h tmr1 : 00004e h 00004f h address ? 16-bit re-load register upper and lower digits ch.0, ch.1 (tmrlr0, tmrlr1) xxxxxxxx b initial value bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wwwwwwwwwwwwwwww xxxxxxxx b xxxxxxxx b xxxxxxxx b tmrlr0 : 00004b h 00004a h tmrlr1 : 00004e h 00004f h address r/w : readable and writable r : read only w : write only x : indeterminate : undefined bits (read value undefined) mb90520 series 45 (2) block diagram internal data bus tmrlr0* 1 mb90520 series 46 6. 16-bit i/o timer the 16-bit i/o timer module consists of two 16-bit free-run timers, two input capture circuits (icu), and eight output comparators (ocu). this module allows two independent waveforms to be output on the basis of the 16-bit free-run timer. input pulse width and external clock periods can, therefore, be measured. ?block diagram internal data bus input capture 0, 1 (icu) 16-bit free-run timer 1, 2 output compare 0, 1 (ocu) dedicated bus dedicated bus mb90520 series 47 (1) 16-bit free-run timer 1, 2 the 16-bit free-run timer consists of a 16-bit up counter, a control register and a communications prescaler register. the value output from the timer counter is used as basic time (base timer) for input capture (icu) and output compare (ocu). ? a counter operation clock can be selected from four internal clocks ( f /4, f /16, f /64 and f /256). ? an interrupt can be generated by overflow of counter value or compare match with ocu compare register 0 and 4. (compare match requires mode settings.) ? the counter value can be initialized to 0000 h by a reset, software clear or compare match with ocu compare register 0 and 4. ? register configuration ? block diagram ? free-run timer data register 1, 2 (tcdt1, tcdt2) ? free-run timer control status register 1, 2 (tccs1, tccs2) ivf reserved r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 stop ivfe clr mode clk0 clk1 bit 3 bit 2 bit 1 bit 0 r/w: readable and writable address tccs1 : 000058 h tccs2 : 000068 h address tcdt1 : 000057 h 000056 h tcdt2 : 000067 h 000066 h bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t15 t14 t13 t12 t11 t10 t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 00000000 b initial value 00000000 b 00000000 b 00000000 b 00000000 b initial value 00000000 b free-run timer data register (tcdt1)* 1 mb90520 series 48 (2) input capture 0, 1 (icu) the input capture (icu) generates an interrupt request to the cpu while storing the current counter value of the 16-bit free-run timer to the icu data register (ipcp) upon input of a trigger edge from the external pin. there are two sets (two channels) of input capture external pins and icu data registers, enabling measurements of a maximum of four events. ? the input capture has two sets of external input pins (in0, in1) and icu registers (ipcp), enabling measurements of a maximum of four events. ? trigger edge direction can be selected from rising/falling/both edges. ? the input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run timer to the icu data register (ipcp). ? the input compare conforms to the extended intelligent i/o service (ei 2 os). ? the input capture ( icu) function is suited for measurements of intervals (frequencies) and pulse-widths. ? register configuration ? icu data register ch.0 ch.1 (ipcp0, ipcp1) address initial value xxxxxxxx b cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r r r rr r r r address initial value xxxxxxxx b cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r r rr r r rr ? icu control status register (ics01) r/w : readable and writable r : read only x : indeterminate ipcp0(upper) : 000051 h ipcp1(upper) : 000053 h address 000054 h initial value 00000000 b icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ipcp0(lower) : 000050 h ipcp1(lower) : 000052 h note: this register holds a 16-bit free-run timer value when the valid edge of the corresponding external pin input waveform is detected. (this register can be word-accessed, but not programmed.) mb90520 series 49 ?block diagram internal data bus edge detection circuit data latch signal latch signal output latch icu data register (ipcp) ipcp0(upper) ipcp0(lower) 16 16 16-bit free-run timer 1, 2 2 2 p20/ic00 pin pin interrupt request #31* icp1 p21/ic01 ipcp1(lower) icp0 ice1 ice0 eg11 eg10 eg01 eg00 interrupt request #32* * : interrupt number icu control status register (ics01) p22/ic10 pin pin p23/ic11 ipcp1(upper) mb90520 series 50 (3) output compare 0, 1 (ocu) the output compare (ocu) is two sets of compare units each consisting of an eight-channel ocu compare register, a comparator and a control register. an interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the ocu compare data register setting value and the counter value of the 16-bit free-run timer. the out pin can be used as a waveform output pin for reversing output upon a match detection or a general- purpose output port for directly outputting the setting value of the cmod bit. ?register c onfiguration cmod ote1 ote0 otd1 otd0 ? ocu control status register ch.01, ch.23, ch.45, ch.67 (ocs01, ocs23, ocs45, ocs67) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w address icp1 icp0 ice1 ice0 cst1 cst0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w c15c14c13c12c11c10c09c08 ? ocu control status register ch.0 to ch.7 (ocs0 to ocs7) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w c07 c06 c05 c04 c03 c02 c01 c00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w : readable and writable x : indeterminate : undefined bits (read value undefined) ch.01 : ocs01 (upper) : 0000063 h ch.23 : ocs23 (upper) : 0000065 h ch.45 : ocs45 (upper) : 000002d h ch.67 : ocs67 (upper) : 000002f h address ch.01 : ocs01 (lower) : 000062 h ch.23 : ocs23 (lower) : 000064 h ch.45 : ocs45 (lower) : 00002c h ch.67 : ocs67 (lower) : 00002e h address ch.0 : ocp0 (upper) : 00005b h ch.1 : ocp1 (upper) : 00005d h ch.2 : ocp2 (upper) : 00005f h ch.3 : ocp3 (upper) : 000061 h ch.4 : ocp4 (upper) : 00000d h ch.5 : ocp5 (upper) : 00001d h ch.6 : ocp6 (upper) : 000035 h ch.7 : ocp7 (upper) : 00006d h address ch.0 : ocp0 (lower) : 00005a h ch.1 : ocp1 (lower) : 00005c h ch.2 : ocp2 (lower) : 00005e h ch.3 : ocp3 (lower) : 000060 h ch.4 : ocp4 (lower) : 00000c h ch.5 : ocp5 (lower) : 00001c h ch.6 : ocp6 (lower) : 000034 h ch.7 : ocp7 (lower) : 00006c h xxx00000 b initial value 0000xx00 b initial value xxxxxxxx b initial value xxxxxxxx b initial value mb90520 series 51 ? block diagram ocu control status register ch. 23 (ocs23) 16-bit free-run timer 1 compare control circuit 3 ocp3 #34* #33* output compare interrupt request output control circuit 3 pin p35/out3 * : interrupt number 2 2 cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 ocu compare register ch. 3 compare control circuit 2 ocp2 ocu compare register ch. 2 compare control circuit 1 ocu compare register ch.1 compare control circuit 0 ocu compare register ch. 0 ocp1 ocp0 internal data bus ocu control status register ch. 01 (ocs01) cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 #36* #35* output compare interrupt request output control circuit 2 output control circuit 1 output control circuit 0 pin p33/out1 pin p34/out2 pin p32/out0 2 2 ? output compare 0 (ocu) mb90520 series 52 * : interrupt number internal data bus compare control circuit 7 pin p73/to1/out7 ? output compare 1(ocu) output control circuit 7 cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 2 2 2 2 ocp7 ocp6 ocp5 ocp4 16-bit free-run timer 2 ocu compare register ch. 7 compare control circuit 6 ocu compare register ch. 6 compare control circuit 5 ocu compare register ch. 5 compare control circuit 4 ocu compare register ch. 4 ocu control status register ch. 45 (ocs45) #25* output compare interrupt request pin p72/ti1/out6 pin p71/to0/out5 pin p70/ti0/out4 output control circuit 6 output control circuit 5 output control circuit 4 ocu control status register ch. 67 (ocs67) #27* output compare interrupt request cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 mb90520 series 53 7. 8/16-bit up/down counter/timer 0, 1 the 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit re-load compare registers, and their controllers. (1) register configuration ccrl0 : 000086 h ccrl1 : 00008a h ? up/down count register 1 (udcr1) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00000000 b d17 d16 d15 d14 d13 d12 d11 d10 rrrrrrrr ? up/down count register 0 (udcr0) address d06 d07 rrrrrrrr bit 7 bit 6 bit 5 bit 4 d04 d05 d02 d03 d00 d01 bit 3 bit 2 bit 1 bit 0 000080 h initial value 00000000 b 000081 h ? re-load compare register 1 (rcr1) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00000000 b d17 d16 d15 d14 d13 d12 d11 d10 wwwwwwww ? re-load compare register 0 (rcr0) address d06 d07 wwwwwwww bit 7 bit 6 bit 5 bit 4 d04 d05 d02 d03 d00 d01 bit 3 bit 2 bit 1 bit 0 000082 h initial value 00000000 b 000083 h ? counter status register 0, 1 (csr0, csr1) address cite cstr r/w r/w r/w r/w r/w r/w r r bit 7 bit 6 bit 5 bit 4 cmpf udie udff ovff udf0 udf1 bit 3 bit 2 bit 1 bit 0 csr0 : 000084 h csr1 : 000088 h initial value 00000000 b ? counter control register 0, 1 (ccrl0, ccrl1) address ctut r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 rlde ucre cgsc udcc cge0 cge1 bit 3 bit 2 bit 1 bit 0 initial value x0000000 b ? counter control register 0 (ccrh0) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00000000 b m16e cdcf cfie clks cms1 cms0 ces1 ces0 r/w r/w r/w r/w r/w r/w r/w r/w 000087 h ? counter control register 1 (ccrh1) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value x0000000 b cdcf cfie clks cms1 cms0 ces1 ces0 r/w r/w r/w r/w r/w r/w r/w 00008b h r/w : readable and writable r : read only w : write only : undefined bits (read value undefined) mb90520 series 54 (2) block diagram ? block diagram of 8/16-bit up/down counter/timer 0 internal data bus rcr0 re-load compare register 0 re-load control circuit up/down count register 0 udcr0 carry/ borrow counter control register 0 (ccrl0) ctut cge1 cge0 ucre udcc rlde cgsc pin edge/level detection circuit counter clear circuit overflow underflow compare control circuit prescaler p24/ain0 pin pin p25/bin0 up/down count clock selector counter status register 0 (csr0) count clock cstr cite udie cmpf ovff udff udf1 udf0 cdcf ces1 ces0 cfie cms1 clks cms0 interrupt request #21* interrupt request #22* counter control register 0 (ccrh0) m16e (to channel 1) (to channel 1) * : interrupt number f : machine clock frequency f p26/zin0/int7 m16e mb90520 series 55 ? block diagram of 8/16-bit up/down counter/timer 1 internal data bus rcr1 re-load compare register 1 re-load control circuit up/down count register 1 udcr1 counter control register 1 (ccrl1) ctut cge1 cge0 ucre udcc rlde cgsc pin counter clear circuit overflow underflow f pin pin p51/sot2/bin1 carry/borrw (from channel 0) up/down count clock selector counter status register 1 count clock (csr1) cstr cite udie cmpf ovff udff udf1 udf0 cdcf ces1 ces0 cfie cms1 clks cms0 interrupt request #29* interrupt request #30* counter control register 1 (ccrh1) (from channel 1) * : interrupt number f : machine clock frequency m16e prescaler p50/sin2/ain1 p52/sck2/zin1 edge/level detection circuit compare control circuit mb90520 series 56 8. extended i/o serial interface 0, 1 the extended i/o serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. for data transfer, you can select lsb first/msb first. (1) register configuration ? serial mode control upper status register 0, 1 (smcsh0, smcsh1) ? serial mode control lower status register 0, 1 (smcsl0, smcsl1) ? serial data register 0, 1 (sdr0, sdr1) address smcsh0 : 000025 h smcsh1 : 000029 h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00000010 b smd2 smd1 smd0 sie sir busy stop strt r/w r/w r/w r/w r/w r r/w r/w address r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bds mode scoe soe bit 3 bit 2 bit 1 bit 0 smcsl0 : 000024 h smcsl1 : 000028 h initial value xxxx0 0 0 0 b address d6 d7 r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 d4 d5 d2 d3 d0 d1 bit 3 bit 2 bit 1 bit 0 sdr0 : 000026 h sdr1 : 00002a h initial value xxxxxxxx b r/w : readable and writable r : read only x : indeterminate : undefined bits (read value undefined) mb90520 series 57 (2) block diagram internal data bus pin (msb first) d0 to d7 d7 to d0 (lsb first) transfer direction selection serial data register (sdr) read write shift clock counter p46/sot1 pin p45/sin1 p50/sin2/ain1 pin pin pin p47/sck1 p52/sck2/zin1 pin control circuit internal clock 210 smd2 smd1 smd0 sie sir busy stop strt mode bds soe scoe interrupt request #15 (smcs0)* #17 (smcs1)* *: interrupt number serial mode control status register (smcsh , l) p51/sot2/bin1 3 mb90520 series 58 9. uart (sci) uart (sci) is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization system). ? data buffer: full-duplex double buffer ? transfer mode:clock synchronized (with start and stop bit) clock asynchronized (start-stop synchronization system) ? baud rate:embedded dedicated baud rate generator external clock input possible internal clock (a clock supplied from 16-bit re-load timer 0 can be used.) ? data length:8 bit (without a parity bit) 7 bit (with a parity bit) ? signal format: nrz (non return to zero) system ? reception error detection: framing error overrun error parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) ? interrupt request: receive interrupt (reception complete, receive error detection) transmit interrupt (transmisson complete) transmit/receive conforms to extended intelligent i/o service (ei 2 os) asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps clk synchronization 1 mbps/500 kbps/250 kbps/125 kbps/62.5 kbps } internal machine clock for 6 mhz, 8 mhz, 10 mhz, 12 mhz and 16 mhz mb90520 series 59 (1) register configuration r/w:readable and writable r : read only w:write only x : indeterminate : undefined bits (read value undefined) ? serial control register (scr) pen p sbl cl a/d rec rxe txe address 000021 h ? serial mode register (smr) md1 md0 cs2 cs1 cs0 reserved scke soe address 000020 h ? serial status register (ssr) address 000023 h ? serial input data register (sidr) address 000022 h ? serial output data register (sodr) address 000022 h r/w r/w r/w r/w r/w w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pe ore fre rdrf trde rie tie bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 rr r rrr/wr/w d7 d6 d5 d4 d3 d2 d1 d0 rrrrrr rr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 wwwwww ww bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? communications prescaler control register (cdcr) address 000027 h initial value 00000100 b initial value 00000000 b initial value 00001x00 b initial value xxxxxxxx b initial value xxxxxxxx b initial value 0xxx1111 b md div3 div2 div1 div0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w mb90520 series 60 (2) block diagram clock selector dedicated baud rate generator external clock p42/sck0 pin p42/sin0 receive condition decision circuit smr register scr register ssr register receive clock receive control circuit start bit detection circuit receive bit counter receive parity counter shift register for reception sidr sodr transmit clock transmit control circuit transmit start circuit transmit bit counter transmit parity counter shift register for transmission receive interrupt signal #37* transmit interrupt signal #39* p43/sot0 start transmission to e i 2 os reception error generation signal (to cpu) internal data bus md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe fre rdrf tdre rie tie * : interrupt number control bus reception complete ore pin pin 16-bit re-load timer 0 mb90520 series 61 10. dtp/external interrupt circuit the dtp (data transfer peripheral), which is located between the peripheral circuit outside the device and the f 2 mc-16lx cpu, receives an interrupt request or dma request generated by the external peripheral circuit* for transmission to the f 2 mc-16lx cpu. it is used to activate the intelligent i/o service or interrupt processing. as with request levels, two types of h and l can be selected for the intelligent i/o service. rising and falling edges as well as h and l can be selected for an external interrupt request. * : the external peripheral circuit is connected outside the mb90520 series device. (1) register configuration ? dtp/interrupt factor register (eirr) address 000031 h er7 er6 er5 er4 er3 er2 er1 er0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w address 000030 h en7 en6 en5 en4 en3 en2 en1 en0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b address elvr (lower) : 000032 h lb3 la3 lb2 la2 lb1 la1 lb0 la0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b ? dtp/interrupt enable register (enir) r/w: readable and writable x : indeterminate address elvr (upper) : 000033 h lb7 la7 lb6 la6 lb5 la5 lb4 la4 initial value 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w ? request level setting register (elvr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 mb90520 series 62 (2) block diagram request level setting register (elvr) lb7 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 2 222 22 level edge selector 7 level edge selector 5 level edge selector 3 level edge selector 1 level edge selector 6 level edge selector 4 level edge selector 2 level edge selector 0 dtp/external interrupt input detection circuit er7 er0 er6er5er4er3er2er1 en7 en0 en6en5en4en3en2en1 dtp/interrupt factor register (eirr) #24* #20* #18* #13* dtp/interrupt enable register (enir) 22 internal data bus pin p26/zin0/int7 pin p06/int6 pin pin pin pin pin *: interrupt number p05/int5 p04/int4 p03/int3 p02/int2 p01/int1 p00/int0 interrupt request signal mb90520 series 63 11. wake-up interrupt wake-up interrupts transmit interrupt request (l level) generated by peripheral equipment located between external peripheral devices and the f 2 mc-16lx cpu to the cpu and invoke interrupt processing. the interrupt does not conform to the exterded intelligent i/o service (ei 2 os). (1) register configuration (2) block diagram bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ? wake-up interrupt flag register (eifr) address 00000f h wif initial value xxxxxxx0 b r/w ? wake-up interrupt enable register (eicr) en7 en6 en5 en4 en3 en2 en1 en0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address 00001f h initial value 00000000 b wwwwwwww r/w: readable and writable w : write only : undefined bits (read value undefined) p10/wi0 pin wake-up interrupt enable register (eicr) interrupt request detection circuit internal data bus wake-up interrupt flag register (eifr) *: interrupt number wake-up interrupt request #16* pin pin pin pin pin pin pin en7 en6 en5 en4 en3 en2 en1 en0 wif p11/wi1 p12/wi2 p13/wi3 p14/wi4 p15/wi5 p16/wi6 p17/wi7 mb90520 series 64 12. delayed interrupt generation module the delayed interrupt generation module generates interrupts for switching tasks. by using this module, hardware interrupt requests to the cpu can be generated and cancelled using software. this module does not conform to the extended intelligent i/o service (ei 2 os). (1) register configuration the dirr is the register used to control delay interrupt request generation/cancellation. programming this register with 1 generates a delay interrupt request. programming this register with 0 cancels a delay interrupt request. upon a reset, an interrupt is canceled. the undefined bit area can be programmed with either 0 or 1. for future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) block diagram ? delayed interrupt factor generation/cancellation register (dirr) address 00009f h r0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w initial value xxxxxxx0 b r/w: readable and writable : undefined bits (read value undefined) note: upon a reset, an interrupt is cancelled. delayed interrupt factor generation/ cancellation register (dirr) *: interrupt number s factor r latch r0 internal data bus interrupt request signal #42* mb90520 series 65 13. 8/10-bit a/d converter the 8/10-bit a/d converter converts analog voltage input to the analog input pins (input voltage) to digital values (a/d conversion) and has the following features: ? minimum conversion time: minimum 15.0 m s (at machine clock frequency of 16 mhz, including sampling time) ? minimum sampling period: 4 m s/8 m s (at machine clock frequency of 16 mhz) ? compare time: 99/176 machine cycles per channel (99 machine cycles are used for a machine clock frequency below 10 mhz.) ? conversion method: rc successive approximation method with a sample and hold circuit ? 8/10-bit resolution ? analog input pins: selectable from eight channels by software single conversion mode: selects and converts one channel. scan conversion mode: converts two or more successive channels. up to eight channels can be programmed. continuous conversion mode: repeatedly converts specified channels. stop conversion mode: stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously). ? interrupt requests can be generated and the extended intelligent i/o service (ei 2 os) can be started after the end of a/d conversion. furthermore, a/d conversion result data can be transferred to the memory, enabling efficient continuous processing. ? when interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. ? starting factors for conversion: selectable from software activation, external trigger (falling edge) and timer (rising edge). mb90520 series 66 (1) register configuration r/w: readable and writable r : read only w : write only x : indeterminate : undefined bits (read value undefined) ? a/d control status register upper digits (adcs2) address 000037 h busy int inte paus sts1 sts0 strt reserved bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w w r/w address 000036 h md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w ? a/d control status register lower digits (adcs1) ? a/d data register upper digits (adcr2) initial value 00000000 b initial value 00000000 b address 000039 h selb st1 st0 ct1 ct0 (d9) (d8) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 wwwww r r address 000038 h d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rrrrrrrr ? a/d data register lower digits (adcr1) initial value xxxxxxxx b initial value 00001xxx b mb90520 series 67 (2) block diagram to : 16-bit re-load timer channel 1 output * : interrupt number f : machine clock frequency interrupt request #11* clock selector decoder sample hold circuit control circuit 8-bit d/a converter analog channel selector comparator a/d data register (adcr) avrh, avrl av cc av ss p27/adtg p73/to1/out7 a/d control status register (adcs) busy int inte paus sts1 sts0 strt reserved md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 selb st1st0ct1ct0(d9)(d8)d7d6d5d4d3d2d1d0 p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 2 6 f internal data bus mb90520 series 68 14. 8-bit d/a converter the 8-bit d/a converter, which is based on the r-2r system, supports 8-bit resolution mode. it contains two channels, each of which can be controlled in terms of output by the d/a control register. (1) register configuration bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? d/a converter data register ch.0 (dadr0) address 00003a h da17 da16 da15 da14 da13 da12 da11 da10 r/w r/w r/w r/w r/w r/w r/w r/w address 00003b h da07 da06 da05 da04 da03 da02 da01 da00 r/w r/w r/w r/w r/w r/w r/w r/w r/w: readable and writable x : indeterminate : undefined bits (read value undefined) ? d/a converter data register ch.1 (dadr1) ? d/a control register 0 (dacr0) initial value xxxxxxxx b initial value xxxxxxxx b address 00003c h address 00003d h ? d/a control register 1 (dacr1) initial value xxxxxxx0 b initial value xxxxxxx0 b dae0 dae1 r/w r/w mb90520 series 69 ?block diagram da17 internal data bus internal data bus d/a converter data register ch.1 (dadr1) d/a converter data register ch.0 (dadr0) da16 da15 da14 da13 da12 da11 da10 da07 da06 da05 da04 da03 da02 da01 da00 d/a converter 1 d/a converter 0 da17 da16 da15 da14 da13 da12 da11 da10 da07 da06 da05 da04 da03 da02 da01 da00 dvrh dvrl 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r dv ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r dv ss pin p54/da1 pin p53/da0 standby control d/a control register 1 (dacr1) standby control d/a control register 0 (dacr0) dae1 dae0 2r 2r mb90520 series 70 15. clock timer the clock timer control register (wtc) controls operation of the clock timer, and time for an interval interrupt. (1) register configuration (2) block diagram ? clock timer control register (wtc) address 0000aa h wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r r/w r/w r/w r/w r/w r/w r/w: readable and writable r : read only x : indeterminate initial value 1x001000 b timer counter lclk power-on reset shift to a hardware stand-by shift to stop mode counter clear circuit interval timer selector clock timer control register (wtc) wdcs to sub-clock stabilization time controller to watchdog timer 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 of of of of of of of sce wtie wtof wtr wtc2 wtc1 wtc0 * : interrupt number of : overflow lclk : sub-clock frequency clock timer interrupt request #22* mb90520 series 71 16.lcd controller/driver the lcd (liquid crystal display) controller/driver, which contains a 16-byte display data memory, controls lcd indication using four common output pins and 32 segment output pins. it can select three types of duty output and directly drive the lcd panel. (1) register configuration bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? lcdc control register 0 (lcr0) address 00006a h reserve d seg5 seg4 reserve d seg3 seg2 seg1 seg0 r/w r/w r/w r/w r/w r/w r/w r/w css lcen vsel bk ms1 ms0 fp1 fp0 r/w r/w r/w r/w r/w r/w r/w r/w ? lcdc control register 1 (lcr1) ? port 7/com pin selection register (lcdcmr) initial value 00000000 b initial value 00010000 b address 00000b h initial value xxxx0000 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 com3 com2 com1 com0 r/w r/w r/w r/w r/w: readable and writable x : indeterminate : undefined bits (read value undefined) ? ram for lcd indication (vram) b7 b6 b5 b4 b3 b2 b1 b0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address 000070 h to 00007f h initial value xxxxxxxx b r/w r/w r/w r/w r/w r/w r/w r/w address 00006b h mb90520 series 72 (2) block diagram hclk : oscillation frequency lclk : sub-clock frequency prescaler internal data bus lcdc control register 0 (lcr0) hclk lclk css lcen vsel bk ms1 ms0 fp1 fp0 reserved seg5 seg4 seg3 seg2 seg1 seg0 lcdc control register 1 (lcr1) timing controller indication ram (16 bytes) common driver segment driver split resistor generator ac controller section pin v0 pin v1 pin v2 pin v3 pin p74/com0 pin p75/com1 pin p76/com2 pin p77/com3 pin seg00 pin seg01 pin seg02 pin p95/seg29 pin p96/seg30 pin p97/seg31 . . . . . . . . . . . . . . . . . . 6 32 2 reserved mb90520 series 73 17. communications prescaler register this register controls machine clock division. output from the communications prescaler register is used for uart (sci) and extended i/o serial interface. the communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) register configuration md div3 div2 div1 div0 ? communications prescaler control register (cdcr) address 000027 h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w initial value 0xxx1 1 1 1 b r/w: readable and writable : undefined bits (read value undefined) mb90520 series 74 18. address match detection function when the address is equal to a value set in the address detection register, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code (01h). as a result, when the cpu executes a set instruction, the int9 instruction is executed. processing by the int#9 interrupt routine allows the program patching function to be implemented. two address detection registers are supported. an interrupt enable bit is prepared for each register. if the value set in the address detection register matches an address and if the interrupt enable bit is set at 1, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code. (1) register configuration ? program address detection register 0 to 2 (padr0) bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 initial value xxxxxxxx b r/w: readable and writable x : indeterminate : undefined bits (read value undefined) address padr0 (high order address) : 001ff2 h r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value xxxxxxxx b address padr0 (middle order address) : 001ff1 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr0 (low order address) : 001ff0 h r/w r/w r/w r/w r/w r/w r/w r/w bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 initial value xxxxxxxx b address padr1 (high order address) : 001ff5 h r/w r/w r/w r/w r/w r/w r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value xxxxxxxx b address padr1 (middle order address) : 001ff4 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (low order address) : 001ff3 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 00000000 b address 00009e h r/w r/w r/w r/w r/w r/w r/w r/w ? program address detection register 3 to 5 (padr1) ? program address detection control status register (pacsr) reserved ad1e reserved ad0e reserved reserved reserved reserved mb90520 series 75 (2) block diagram internal data bus address latch enable bit f 2 mc-16lx cpu core address detection register compare int9 instruction mb90520 series 76 19. rom mirroring function selection module the rom mirror function select module enables the rom data from the ff bank to be read also from the 00 bank. (1) register configuration note: do not access this register during operation at addresses 004000 h to 00ffff h . (2) block diagram ? rom mirroring function selection register (romm) address 00006f h mi bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w : write only : undefined bits (read value undefined) initial value xxxxxxx1 b w rom mirroring function selection register (romm) address area ff bank 00 bank rom data internal data bus address mb90520 series 77 20. low-power consumption (stand-by) mode the f 2 mc-16lx has the following cpu operating modes configured by selection of an operating clock and clock operation control. ?clock mode pll clock mode : a mode in which the cpu and peripheral equipment are driven by pll-multiplied oscillation clock. main clock mode: a mode in which the cpu and peripheral equipment are driven by drivided-by-2 of the oscillation clock. the pll multiplication circuits stops in the main clock mode. ? sub-clock mode the sub-clock mode causes the cpu to operate only with the sub-clock. this mode uses the sub-clock frequency divided by four as the operating clock frequency while stopping the main clock and pll clock. ? cpu intermittent operation mode the cpu intermittent operation mode is a mode for reducing power consumption by operating the cpu intermittently while external bus and peripheral functions are operated at a high speed. ? hardware stand-by mode the hardware standby mode is a mode for reducing power consumption by stopping clock supply to the cpu by the low-power consumption control circuit (sleep mode), stopping clock supplies to the cpu and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). of these modes, modes other than the pll clock mode are low power consumption modes. (1) register configuration ? clock select register (ckscr) address 0000a1 h scm mcm ws1 ws0 scs mcs cs1 cs0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r r r/w r/w r/w r/w r/w r/w address 0000a0 h stp slp spl rst tmd cg1 cg0 ssr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w w r/w w w r/w r/w r/w r/w: readable and writable r : read only w : write only ? low-power consumption mode control register (lpmcr) initial value 00011000 b initial value 11111100 b mb90520 series 78 (2) block diagram stp standby control circuit slp spl rst tmd cg1 cg0 ssr low-power consumption mode control register (lpmcr) hardware standby reset interrupt sq r sq r sq r sq r 2 2 2 cpu intermittent operation cycle selector cpu clock control circuit peripheral clock control circuit cpu operation clock peripheral function operation clock clock mode sleep signal stop signal machine clock clock selector pll multiplication circuit clock select register (ckscr) scm mcm ws1 ws0 scs mcs cs1 cs0 timebase timer to watchdog timer clock timer sub-clock oscillator sub-clock oscillation clock clock oscillator main clock divided- by-2 divided- by-2048 divided- by-4 divided- by-4 divided- by-8 divided- by-1024 divided- by-8 divided- by-2 divided- by-2 oscillation stabilization time selector pin x0 pin x1 pin x0a pin x1a s : set r : reset q : output mb90520 series 79 21.clock monitor function the clock monitor function outputs the frequency-divided machine clock signal (for monitoring purposes) from the ckot pin. (1) register configuration (2) block diagram ? clock output enable register address 00003e h initial value xxxxxxx1 b r/w:readable and writable :undefined bits (read value undefined) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ???? cken frq2 frq1 frq0 r / wr / wr / w ? ? ? ? r / w internal data bus divider circuit cken fqr2 fqr1 fqr0 p31/ckot f f : machine clock frequency mb90520 series 80 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) *1: av cc , avrh, avrl, and dv cc shall never exceed v cc . avrl shall never exceed avrh. *2: v cc 3 av cc 3 dv cc 3 3.0v *3: v i and v o shall never exceed v cc + 0.3 v. *4: the maximum output current is a peak value for a corresponding pin. *5: average output current is an average current value observed for a 100 ms period for a corresponding pin. *6: total average current is an average current value observed for a 100 ms period for all corresponding pins. note: average output current = operating current operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 6.0 v av cc v ss C 0.3 v ss + 6.0 v *1 avrh, avrl v ss C 0.3 v ss + 6.0 v *1 dv cc v ss C 0.3 v ss + 6.0 v *2 input voltage v i v ss C 0.3 v cc + 6.0 v *3 output voltage v o v ss C 0.3 v cc + 6.0 v *3 l level maximum output current i ol ? 15 ma *4 l level average output current i olav ? 4ma*5 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma *6 h level maximum output current i oh ? C15 ma *4 h level average output current i ohav ? C4 ma *5 h level total maximum output current s i oh ? C100 ma h level total average output current s i ohav ? C50 ma *6 power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c mb90520 series 81 2. recommended operating conditions (av ss = v ss = 0.0 v) * : use a ceramic capacitor or a capacitor with equivalent frequency characteristics. the smoothing capacitor to be connected to the v cc pin must have a capacitance value higher than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 5.5 v normal operation (MB90522, mb90523) v cc 4.0 5.5 v normal operation (mb90f523) guaranteed frequency = 10 mhz at 4.0 v to 4.5v v cc 3.0 5.5 v retains status at the time operation stops smoothing capacitor c s 0.1 1.0 m f* operating temperature t a C40 +85 c ? c pin diagram c s c mb90520 series 82 3. dc characteristics (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ihs p20 to p27, p30 to p37, p53, p54, p70 to p77, p80 to p87, pa 0 t o pa 7 , v cc = 3.0 v to 5.5 v ( mb90523) v cc = 4.0 v to 5.5 v ( mb90f523) 0.8 v cc v cc + 0.3 v v ihm md0 to md2 v cc C 0.3 v cc + 0.3 v l level input voltage v ils p20 to p27, p30 to p37, p53, p54, p70 to p77, p80 to p87, pa 0 t o pa 7 , v ss C 0.3 0.2 v cc v v ilm md0 to md2 v ss C 0.3 v ss + 0.3 v h level output voltage v oh other than p90 to p97 v cc = 4.5 v, i oh = C2.0 ma v cc C 0.5 v l level output voltage v ol all output pins v cc = 4.5 v, i ol = 2.0 ma 0.4v open-drain output leakage current i leak output pin p90 to p97 0.15 m a input leakage current i il other than p90 to p97 v cc = 5.5 v, v ss < v i < v cc C5 5 m a pull-up resistance r up p00 to p07, p10 to p17, p40 to p47, rst , md0, md1 15 30 100 k w pull-down resistance r down md2 15 30 100 k w mb90520 series 83 (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. power supply current* i cc v cc internal operation at 16 mhz v cc at 5.0 v normal operation 3040ma MB90522, mb90523 i cc v cc 85 130 ma mb90f523 i cc v cc internal operation at 16 mhz v cc at 5.0 v a/d converter operation 3545ma MB90522, mb90523 i cc v cc 90 140 ma mb90f523 i cc v cc internal operation at 16 mhz v cc at 5.0 v d/a converter operation 4050ma MB90522, mb90523 i cc v cc 95 145 ma mb90f523 i cc v cc when data is written or erased in flash mode 95 140 ma mb90f523 i ccs v cc internal operation at 16 mhz v cc at 5.0 v in sleep mode 712ma MB90522, mb90523 i ccs v cc 25 30 ma mb90f523 i ccl v cc internal operation at 8 khz v cc at 5.0 v t a = +25 c subsystem operation 0.11.0ma MB90522, mb90523 i ccl v cc 4 7 ma mb90f523 i ccls v cc internal operation at 8 khz v cc at 5.0 v t a = +25 c in subsleep mode 3050 m a MB90522, mb90523 i ccls v cc 0.1 1 ma mb90f523 i cct v cc internal operation at 8 khz v cc at 5.0 v t a = +25 c in clock mode 1530 m a MB90522, mb90523 i cct v cc 3050 m a mb90f523 i cch v cc t a = +25 c in stop mode 520 m a MB90522, mb90523 i cch v cc 0.110 m a mb90f523 input capacitance c in other than av cc , av ss , c, v cc , v ss 10 80 pf mb90520 series 84 (continued) (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : the current value is preliminary and may be subject to change for enhanced characteristics without previous notice.the power supply current is measured with an external clock. parameter symbol pin name condition value unit remarks min. typ. max. lcd split resistor r lcd v0 to v1, v1 to v2, v2 to v3 50 100 200 k w output impedance for com0 to com3 r vcom com0 to com3 v1 to v3 = 5.0 v 2.5k w output impedance for seg00 to seg31 r vseg seg00 to seg31 15k w lcdc leak current i lcdc v0 to v3, com1 to com3, seg00 to seg31 5 m a mb90520 series 85 4. ac characteristics (1) reset, hardware standby input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 4 t cp *ns hardware standby input time t hstl hst 4 t cp *ns 0.2 v cc t rstl , t hstl rst hst 0.2 v cc ? measurement conditions for ac ratings pin c l c l is a load capacitance connected to a pin under test. c l of 80 pf must be connected to address data bus (ad15 to ad00). mb90520 series 86 (2) specification for power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : v cc must be kept lower than 0.2 v before power-on. notes: ? the above ratings are values for causing a power-on reset. ? there are internal registers which can be initialized only by a power-on reset. apply power according to this rating to ensure initialization of the registers. parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 0.05 30 ms * power supply cut-off time t off v cc 4ms due to repeated operations v cc t off 0.2 v 2.7 v 0.2 v 0.2 v t r v ss sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage when the pll clock is not in use. if the voltage drops 1 v or less per second, however, the pll clock may be used. v cc 0.2 v it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. mb90520 series 87 (3) clock timings (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : the frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied pll signal is locked. the pll frequency deviation changes periodically from the preset frequency (about clk (1cyc to 50 cyc), thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals). parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f c x0, x1 3 16 mhz f c x0, x1 4.0 v to 4.5 v 3 10 mhz mb90f523 f cl x0a, x1a 32.768 khz clock cycle time t hcyl x0, x1 62.5 333 ns t hcyl x0, x1 4.0 v to 4.5 v 100 333 ns mb90f523 t lcyl x0a, x1a 30.5 m s input clock pulse width p wh , p wl x0 10 ns recommended duty ratio of 30% to 70% p wlh , p wll x0a 15.2 m s input clock rising/falling time t cr , t cf x0, x0a 5 ns external clock operation internal operating clock frequency f cp 1.5 16 mhz when the main clock is used f cp 4.0 v to 4.5 v 1.5 10 mhz when the main clock is used f lcp 8.192khz when the subclock is used internal operating clock cycle time t cp 62.5 333 ns when the main clock is used t cp 4.0 v to 4.5 v 100 333 ns when the main clock is used t lcp 122.1 m s when the subclock is used frequency fluctuation rate locked d f5%* | a | f o center frequency + C + a f o C a d f = 100 (%) mb90520 series 88 ? x0, x1 clock timing p wh 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc p wl t cf t cr t hcyl 0.2 v cc ? x0a, x1a clock timing p wlh 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc p wll t cf t cr t lcyl 0.2 v cc x0 x0a ? pll operation guarantee range relationship between internal operating clock frequency and power supply voltage 18 3 16 (mhz) internal clock f cp 5.5 4.5 4.0 3.3 3.0 (v) mb90f523 operation guarantee range pll operation guarantee range relationship between oscillating frequency and internal operating clock frequency (mhz) multiplied -by-4 not multiplied oscillation clock f c 4 8 12 16 (mhz) 16 12 8 4 3 2 12 power supply voltage v cc internal clock f cp 10 MB90522,mb90523 operation guarantee range 3 2 16 multiplied -by-3 multiplied -by-2 multiplied -by-1 mb90v520 operation guarantee range mb90520 series 89 the ac ratings are measured for the following measurement reference voltages. ? input signal waveform ? output signal waveform 0.8 v cc 0.2 v cc hystheresis input pin 0.7 v cc 0.3 v cc pins other than hystheresis input/md input hystheresis input pin 2.4 v cc 0.8 v cc mb90520 series 90 (4) recommended resonator manufacturers (continued) ? sample application of ceramic resonator xtal c 1 c 2 x0 r x1 * ? mask rom product (MB90522, mb90523) resonator manufacturer resonator frequency (mhz) c 1 (pf) c 2 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 not required csa4.00mg040 4.00 100 100 not required csa8.00mtz 8.00 30 30 not required csa16.00mxz040 16.00 15 15 not required csa32.00mxz040 32.00 5 5 not required tdk corporation ccr3.52mc3 to ccr6.96mc3 3.52 to 6.96 built-in built-in not required ccr7.0mc5 to ccr12.0mc5 7.00 to 12.00 built-in built-in not required ccr20.0msc6 to ccr32.0msc6 20.00 to 32.00 built-in built-in not required mb90520 series 91 (continued) ? flash rom product (mb90f523) inquiry:murata mfg. co., ltd.. ? murata electronics north america, inc.: tel 1-404-436-1300 ? murata europe management gmbh: tel 49-911-66870 ? murata electronics singapore (pte.): tel 65-758-4233 tdk corporation ? tdk corporation of america chicago regional office: tel 1-708-803-6100 ? tdk electronics europe gmbh components division: tel 49-2102-9450 ? tdk singapore (pte) ltd.: tel 65-273-5022 ? tdk hong kong co., ltd.: tel 852-736-2238 ? korea branch, tdk corporation: tel 82-2-554-6636 resonator manufacturer resonator frequency (mhz) c 1 (pf) c 2 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 not required csa4.00mg040 4.00 100 100 not required csa8.00mtz 8.00 30 30 not required csa16.00mxz040 16.00 15 15 not required csa32.00mxz040 32.00 5 5 not required tdk corporation ccr3.52mc3 to ccr6.96mc3 3.52 to 6.96 built-in built-in not required ccr7.0mc5 to ccr12.0mc5 7.0 to 12.0 built-in built-in not required ccr20.0msc6 to ccr32.0msc6 20.0 to 32.0 built-in built-in not required mb90520 series 92 (5) uart (sci) timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. notes: ? these are ac ratings in the clk synchronous mode. ?c l is the load capacitor value connected to pins while testing. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck0 to sck2 internal shift clock mode c l = 80 pf + 1 ttl for an output pin 8 t cp *ns sck ? sot delay time t slov sck0 to sck2, sot0 to sot2 C 80 80 ns valid sin ? sck - t ivsh sck0 to sck2, sin0 to sin2 100 ns sck - ? valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns serial clock h pulse width t shsl sck0 to sck2 external shift clock mode c l = 80 pf + 1 ttl for an output pin 4 t cp *ns serial clock l pulse width t slsh sck0 to sck2 4 t cp *ns sck ? sot delay time t slov sck0 to sck2 sot0 to sot2 150 ns valid sin ? sck - t ivsh sck0 to sck2, sin0 to sin2 60 ns sck - ? valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns mb90520 series 93 ? internal shift clock mode ? external shift clock mode sck 2.4 v 0.8 v sot sin sck sot sin 0.8 v 2.4 v 0.2 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc t scyc t ivsh t shix t slov t slsh t shsl t ivsh t shix t slov mb90520 series 94 (6) timer input timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. (7) timer output timing (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. max. input pulse width t tiwh , t tiwl ic00,ic01,ic10, ic11,ti0, ti1 4 t cp *ns parameter symbol pin name condition value unit remarks min. max. clk - ? t out transition time t to out0 to out3, pg00, pg01,pg10, pg11 30ns t tiwh 0.8 v cc 0.2 v cc t tiwl 0.8 v cc 0.2 v cc in clk t to 2.4 v t out 2.4 v 0.8 v mb90520 series 95 5. a/d converter (av cc = v cc = 5.0 v 10%, av ss = v ss = 0.0 v, 3.0 v avrh C avrl, t a = C40 c to +85 c) * : for t cp (internal operating clock cycle time), refer to (3) clock timings. parameter symbol pin name condition value unit min. typ. max. resolution 8/10bit total error 5.0 lsb non-linear error 2.5 lsb differential linearity error 1.9 lsb zero transition voltage v ot an0 to an7 av ss C3.5 lsb +0.5 lsb av ss +4.5 lsb mv full-scale transition voltage v fst an0 to an7 avrh C6.5lsb avrh C1.5 lsb avrh +1.5 lsb mv conversion time v cc = 5.0 v 10% at machine clock of 16 mhz 240 t cp * ns sampling time v cc = 5.0 v 10% at machine clock of 16 mhz 64 t cp * ns analog port input current i ain an0 to an7 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl + 2.7 av cc v avrl 0 avrh C2.7 v power supply current i a av cc 5ma i ah av cc supply current when cpu stopped and 8/10-bit a/d converter not in operation (v cc = av cc = avrh = 5.0 v) 5 m a reference voltage supply current i r avrh 400 m a i rh avrh supply current when cpu stopped and 8/10-bit a/d converter not in operation (v cc = av cc = avrh = 5.0 v) 5 m a offset between channels an0 to an7 4lsb mb90520 series 96 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error, full-scale transition error and linearity error. (continued) total error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh actual conversion characteristics d i g i t a l o u t p u t v nt (measured value) 0.5 lsb actual conversion characteristics theoretical characteristics 0.5 lsb {1 lsb (n C 1) + 0.5 lsb} [v] avrh C avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb [v] v fst (theoretical value) = avrh C 1.5 lsb [v] total error for digital output n [lsb] v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb = v nt : voltage at a transition of digital output from (n C 1) to n mb90520 series 97 (continued) 7. notes for a/d conversion analog inputs should have external circuit impedance of approximately 5 k w or less. external capacitance, if used, should be several thousand times the level of the chips internal capacitance in consideration of the effects of partial potential between the external and internal capacitance. if the impedance of the external circuit is too high, the analog voltage sampling interval may be insufficient (using a sampling interval of 4.00 m s and a machine clock frequency of 16 mhz). ?error the smaller | avrh C avrl | is, the greater the error is. linearity error n + 1 n n C 1 n C 2 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh analog input avrl avrh actual conversion characteristics v ot (mesured value) v fst (measured value) actual conversion characteristics v nt {1 lsb (n C 1) + v ot } theoretical characteristics d i g i t a l o u t p u t d i g i t a l o u t p u t differential linearity error theoretical characteristics v (n + 1)t (measured value) actual conversion characteristics v nt (measured value) actual conversion characteristics linearity error of digital output n v ot : voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h [lsb] v nt C {1 lsb (n C 1) + v ot } 1 lsb = [v] v fst C v ot 1022 = 1 lsb C 1 lsb [lsb] v (n + 1)t C v nt 1 lsb = differential linearity error of digital n (measured value) ? block diagram of analog input circuit model note: listed values must be considered standards. comparator analog input c MB90522, mb90523 r on : approx. 1.5 k w c: approx. 30 pf mb90f523 r on : approx. 3.0 k w c: approx. 65 pf r on mb90520 series 98 8. d/a converter (av cc = v cc = 5.0 v 10%, av ss = v ss = dv ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name value unit remarks min. typ. max. resolution 8 bit differential linearity error 0.9 lsb absolute accuracy 1.2 % linearity error 1.5 lsb conversion time 10 20 m s load capacitance: 20 pf analog reference voltage dv cc v ss + 3.0 av cc v reference voltage supply current i dvr dv cc 300 m a i dvrs dv cc 10 m a in sleep mode analog output impedance 20k w mb90520 series 99 n example characteristics (1) power supply current (mb90523) 35 30 25 20 15 10 5 v cc (v) fc = 16 mhz 3.0 4.0 i cc C t a t a ( c) C20 i cc (ma) i cc C v cc i ccs (ma) i ccs C v cc 5.0 6.0 fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz 10 9 8 7 6 5 4 3 2 1 fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz v cc (v) 3.0 4.0 5.0 6.0 35 30 25 20 15 10 5 fc = 16 mhz i cc (ma) fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz +10 +40 +70 +100 v cc = 5.0 v v cc = 5.0 v i ccs C t a i ccs (ma) 10 9 8 7 6 5 4 3 2 1 t a ( c) C20 +10 +40 +70 +100 fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz i ccl C v cc 160 140 120 100 80 60 40 20 i ccl ( m a) v cc (v) 3.0 4.0 5.0 6.0 fc = 8 khz fc = 8 khz i ccls C v cc 70 60 50 40 30 20 10 i ccls (ma) v cc (v) 3.0 4.0 5.0 6.0 t a = +25 c t a = +25 c t a = +25 c t a = +25 c mb90520 series 100 35 30 25 20 15 10 5 fc (mhz) v cc = 3.0 v 4.0 6.0 i cc (ma) i cc C fc 8.0 16.0 t a = +25 c v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v i ccs (ma) i ccs C fc 10 9 8 7 6 5 4 3 2 1 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a = +25 c i cct C v cc i cct ( m a) 20 18 16 14 12 10 8 6 4 2 t a = +25 c v cc (v) 3.0 4.0 5.0 6.0 fc = 8 khz 12.0 fc (mhz) 4.0 6.0 8.0 16.0 12.0 i cch C v cc i cch ( m a) 10 9 8 7 6 5 4 3 2 1 t a = +25 c v cc (v) 3.0 4.0 5.0 6.0 i cct C t a i cct ( m a) 10 9 8 7 6 5 4 3 2 1 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 i cch C t a i ccl ( m a) 10 9 8 7 6 5 4 3 2 1 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 mb90520 series 101 (2) power supply current (mb90f523) i ccl C t a i ccl ( m a) 20 18 16 14 12 10 8 6 4 2 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 i cc C v cc i cc (ma) 140 120 100 80 60 40 20 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 v cc (v) fc = 16 mhz 3.0 4.0 5.0 6.0 fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz t a = +25 c i ccs C v cc i ccs (ma) 40 35 30 25 20 15 10 5 v cc (v) fc = 16 mhz 3.0 4.0 5.0 6.0 fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz t a = +25 c i ccls C t a i ccls ( m a) 14 12 10 8 6 4 2 t a ( c) C20 +10 +40 +70 +100 i ccs C t a i ccs (ma) 40 35 30 25 20 15 10 5 fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz fc = 16 mhz fc = 12.5 mhz fc = 10 mhz fc = 8 mhz fc = 5 mhz fc = 4 mhz fc = 2 mhz t a ( c) C20 +10 +40 +70 +100 i cc C t a i cc (ma) 120 100 80 60 40 20 v cc = 5.0 v v cc = 5.0 v mb90520 series 102 i ccls ( m a) i ccs C v cc 200 180 160 140 120 100 80 60 40 20 fc = 8 mhz v cc (v) 3.0 4.0 5.0 6.0 t a = +25 c 120 100 80 60 40 20 fc (mhz) 4.0 i cc (ma) i cc C fc 8.0 16.0 t a = +25 c 12.0 t a = +25 c fc (mhz) 4.0 8.0 16.0 12.0 i ccs C fc i ccs (ma) 40 35 30 25 20 15 10 5 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v i cct C v cc i cct ( m a) 50 40 30 20 10 t a = +25 c v cc (v) 3.0 4.0 5.0 6.0 fc = 8 khz v cc (v) 3.0 4.0 5.0 6.0 i cch C v cc i cch ( m a) 10 9 8 7 6 5 4 3 2 1 t a = +25 c mb90520 series 103 i cct C t a i cct ( m a) 10 9 8 7 6 5 4 3 2 1 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 i cch C t a i cch ( m a) 10 9 8 7 6 5 4 3 2 1 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 i ccls C t a i ccls ( m a) 20 18 16 14 12 10 8 6 4 2 v cc = 3.0 v v cc = 2.5 v v cc = 6.0 v v cc = 5.5 v v cc = 5.0 v v cc = 4.5 v v cc = 4.0 v v cc = 3.5 v t a ( c) C20 +10 +40 +70 +100 mb90520 series 104 n ordering information part number package remarks mb90523pff MB90522pff mb90f523pff 120-pin plastic lqfp (fpt-120p-m05) mb90523pfv MB90522pfv mb90f523pfv 120-pin plastic qfp (fpt-120p-m13) mb90520 series 105 n package dimensions c 1995 fujitsu limited f120013s-2c-3 details of "a" part details of "b" part 0.50?.20(.020?008) 0 10 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 22.60?.20(.890?008)sq 20.00?.10(.787?004)sq 0.50(.0197) 0.20?.10 (.008?004) 0.08(.003) m 0.125?.05 (.005?002) 0.05(.002)min (stand off) 21.60 14.50 (.850) nom (.571) ref 0.10(.004) "a" "b" 30 31 60 61 90 91 120 1 lead no. index 3.85(.152)max (mounting height) dimensions in mm (inches) c 1998 fujitsu limited f120006s-3c-4 0.07(.003) m index 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 130 31 60 91 120 61 90 lead no. (stand off) 0.10?.10 (.004?004) 0.25(.010) (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 (mounting height) 0~8 details of "a" part 1.50 +0.20 ?.10 +.008 ?004 .059 "a" 0.40(.016) 0.16?.03 (.006?001) 0.145?.055 (.006?002) 0.08(.003) (fpt-120p-m05) dimensions in mm (inches) 120-pin plastic lqfp 120-pin plastic qfp (fpt-120p-m13) mb90520 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0012 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. |
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